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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef __DTS_MARVELL_PXA1928_CLOCK_H3#define __DTS_MARVELL_PXA1928_CLOCK_H4 5/*6 * Clock ID values here correspond to the control register offset/4.7 */8 9/* apb peripherals */10#define PXA1928_CLK_RTC 0x0011#define PXA1928_CLK_TWSI0 0x0112#define PXA1928_CLK_TWSI1 0x0213#define PXA1928_CLK_TWSI2 0x0314#define PXA1928_CLK_TWSI3 0x0415#define PXA1928_CLK_OWIRE 0x0516#define PXA1928_CLK_KPC 0x0617#define PXA1928_CLK_TB_ROTARY 0x0718#define PXA1928_CLK_SW_JTAG 0x0819#define PXA1928_CLK_TIMER1 0x0920#define PXA1928_CLK_UART0 0x0b21#define PXA1928_CLK_UART1 0x0c22#define PXA1928_CLK_UART2 0x0d23#define PXA1928_CLK_GPIO 0x0e24#define PXA1928_CLK_PWM0 0x0f25#define PXA1928_CLK_PWM1 0x1026#define PXA1928_CLK_PWM2 0x1127#define PXA1928_CLK_PWM3 0x1228#define PXA1928_CLK_SSP0 0x1329#define PXA1928_CLK_SSP1 0x1430#define PXA1928_CLK_SSP2 0x1531 32#define PXA1928_CLK_TWSI4 0x1f33#define PXA1928_CLK_TWSI5 0x2034#define PXA1928_CLK_UART3 0x2235#define PXA1928_CLK_THSENS_GLOB 0x2436#define PXA1928_CLK_THSENS_CPU 0x2637#define PXA1928_CLK_THSENS_VPU 0x2738#define PXA1928_CLK_THSENS_GC 0x2839 40 41/* axi peripherals */42#define PXA1928_CLK_SDH0 0x1543#define PXA1928_CLK_SDH1 0x1644#define PXA1928_CLK_USB 0x1745#define PXA1928_CLK_NAND 0x1846#define PXA1928_CLK_DMA 0x1947 48#define PXA1928_CLK_SDH2 0x3a49#define PXA1928_CLK_SDH3 0x3b50#define PXA1928_CLK_HSIC 0x3e51#define PXA1928_CLK_SDH4 0x5752#define PXA1928_CLK_GC3D 0x5d53#define PXA1928_CLK_GC2D 0x5f54 55#endif56