276 lines · c
1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */2/*3 * Copyright (c) 2022 Collabora Ltd.4 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>5 */6 7#ifndef _DT_BINDINGS_CLK_MT6795_H8#define _DT_BINDINGS_CLK_MT6795_H9 10/* TOPCKGEN */11#define CLK_TOP_ADSYS_26M 012#define CLK_TOP_CLKPH_MCK_O 113#define CLK_TOP_USB_SYSPLL_125M 214#define CLK_TOP_DSI0_DIG 315#define CLK_TOP_DSI1_DIG 416#define CLK_TOP_ARMCA53PLL_754M 517#define CLK_TOP_ARMCA53PLL_502M 618#define CLK_TOP_MAIN_H546M 719#define CLK_TOP_MAIN_H364M 820#define CLK_TOP_MAIN_H218P4M 921#define CLK_TOP_MAIN_H156M 1022#define CLK_TOP_TVDPLL_445P5M 1123#define CLK_TOP_TVDPLL_594M 1224#define CLK_TOP_UNIV_624M 1325#define CLK_TOP_UNIV_416M 1426#define CLK_TOP_UNIV_249P6M 1527#define CLK_TOP_UNIV_178P3M 1628#define CLK_TOP_UNIV_48M 1729#define CLK_TOP_CLKRTC_EXT 1830#define CLK_TOP_CLKRTC_INT 1931#define CLK_TOP_FPC 2032#define CLK_TOP_HDMITXPLL_D2 2133#define CLK_TOP_HDMITXPLL_D3 2234#define CLK_TOP_ARMCA53PLL_D2 2335#define CLK_TOP_ARMCA53PLL_D3 2436#define CLK_TOP_APLL1 2537#define CLK_TOP_APLL2 2638#define CLK_TOP_DMPLL 2739#define CLK_TOP_DMPLL_D2 2840#define CLK_TOP_DMPLL_D4 2941#define CLK_TOP_DMPLL_D8 3042#define CLK_TOP_DMPLL_D16 3143#define CLK_TOP_MMPLL 3244#define CLK_TOP_MMPLL_D2 3345#define CLK_TOP_MSDCPLL 3446#define CLK_TOP_MSDCPLL_D2 3547#define CLK_TOP_MSDCPLL_D4 3648#define CLK_TOP_MSDCPLL2 3749#define CLK_TOP_MSDCPLL2_D2 3850#define CLK_TOP_MSDCPLL2_D4 3951#define CLK_TOP_SYSPLL_D2 4052#define CLK_TOP_SYSPLL1_D2 4153#define CLK_TOP_SYSPLL1_D4 4254#define CLK_TOP_SYSPLL1_D8 4355#define CLK_TOP_SYSPLL1_D16 4456#define CLK_TOP_SYSPLL_D3 4557#define CLK_TOP_SYSPLL2_D2 4658#define CLK_TOP_SYSPLL2_D4 4759#define CLK_TOP_SYSPLL_D5 4860#define CLK_TOP_SYSPLL3_D2 4961#define CLK_TOP_SYSPLL3_D4 5062#define CLK_TOP_SYSPLL_D7 5163#define CLK_TOP_SYSPLL4_D2 5264#define CLK_TOP_SYSPLL4_D4 5365#define CLK_TOP_TVDPLL 5466#define CLK_TOP_TVDPLL_D2 5567#define CLK_TOP_TVDPLL_D4 5668#define CLK_TOP_TVDPLL_D8 5769#define CLK_TOP_TVDPLL_D16 5870#define CLK_TOP_UNIVPLL_D2 5971#define CLK_TOP_UNIVPLL1_D2 6072#define CLK_TOP_UNIVPLL1_D4 6173#define CLK_TOP_UNIVPLL1_D8 6274#define CLK_TOP_UNIVPLL_D3 6375#define CLK_TOP_UNIVPLL2_D2 6476#define CLK_TOP_UNIVPLL2_D4 6577#define CLK_TOP_UNIVPLL2_D8 6678#define CLK_TOP_UNIVPLL_D5 6779#define CLK_TOP_UNIVPLL3_D2 6880#define CLK_TOP_UNIVPLL3_D4 6981#define CLK_TOP_UNIVPLL3_D8 7082#define CLK_TOP_UNIVPLL_D7 7183#define CLK_TOP_UNIVPLL_D26 7284#define CLK_TOP_UNIVPLL_D52 7385#define CLK_TOP_VCODECPLL 7486#define CLK_TOP_VCODECPLL_370P5 7587#define CLK_TOP_VENCPLL 7688#define CLK_TOP_VENCPLL_D2 7789#define CLK_TOP_VENCPLL_D4 7890#define CLK_TOP_AXI_SEL 7991#define CLK_TOP_MEM_SEL 8092#define CLK_TOP_DDRPHYCFG_SEL 8193#define CLK_TOP_MM_SEL 8294#define CLK_TOP_PWM_SEL 8395#define CLK_TOP_VDEC_SEL 8496#define CLK_TOP_VENC_SEL 8597#define CLK_TOP_MFG_SEL 8698#define CLK_TOP_CAMTG_SEL 8799#define CLK_TOP_UART_SEL 88100#define CLK_TOP_SPI_SEL 89101#define CLK_TOP_USB20_SEL 90102#define CLK_TOP_USB30_SEL 91103#define CLK_TOP_MSDC50_0_H_SEL 92104#define CLK_TOP_MSDC50_0_SEL 93105#define CLK_TOP_MSDC30_1_SEL 94106#define CLK_TOP_MSDC30_2_SEL 95107#define CLK_TOP_MSDC30_3_SEL 96108#define CLK_TOP_AUDIO_SEL 97109#define CLK_TOP_AUD_INTBUS_SEL 98110#define CLK_TOP_PMICSPI_SEL 99111#define CLK_TOP_SCP_SEL 100112#define CLK_TOP_MJC_SEL 101113#define CLK_TOP_DPI0_SEL 102114#define CLK_TOP_IRDA_SEL 103115#define CLK_TOP_CCI400_SEL 104116#define CLK_TOP_AUD_1_SEL 105117#define CLK_TOP_AUD_2_SEL 106118#define CLK_TOP_MEM_MFG_IN_SEL 107119#define CLK_TOP_AXI_MFG_IN_SEL 108120#define CLK_TOP_SCAM_SEL 109121#define CLK_TOP_I2S0_M_SEL 110122#define CLK_TOP_I2S1_M_SEL 111123#define CLK_TOP_I2S2_M_SEL 112124#define CLK_TOP_I2S3_M_SEL 113125#define CLK_TOP_I2S3_B_SEL 114126#define CLK_TOP_APLL1_DIV0 115127#define CLK_TOP_APLL1_DIV1 116128#define CLK_TOP_APLL1_DIV2 117129#define CLK_TOP_APLL1_DIV3 118130#define CLK_TOP_APLL1_DIV4 119131#define CLK_TOP_APLL1_DIV5 120132#define CLK_TOP_APLL2_DIV0 121133#define CLK_TOP_APLL2_DIV1 122134#define CLK_TOP_APLL2_DIV2 123135#define CLK_TOP_APLL2_DIV3 124136#define CLK_TOP_APLL2_DIV4 125137#define CLK_TOP_APLL2_DIV5 126138#define CLK_TOP_NR_CLK 127139 140/* APMIXED_SYS */141#define CLK_APMIXED_ARMCA53PLL 0142#define CLK_APMIXED_MAINPLL 1143#define CLK_APMIXED_UNIVPLL 2144#define CLK_APMIXED_MMPLL 3145#define CLK_APMIXED_MSDCPLL 4146#define CLK_APMIXED_VENCPLL 5147#define CLK_APMIXED_TVDPLL 6148#define CLK_APMIXED_MPLL 7149#define CLK_APMIXED_VCODECPLL 8150#define CLK_APMIXED_APLL1 9151#define CLK_APMIXED_APLL2 10152#define CLK_APMIXED_REF2USB_TX 11153#define CLK_APMIXED_NR_CLK 12154 155/* INFRA_SYS */156#define CLK_INFRA_DBGCLK 0157#define CLK_INFRA_SMI 1158#define CLK_INFRA_AUDIO 2159#define CLK_INFRA_GCE 3160#define CLK_INFRA_L2C_SRAM 4161#define CLK_INFRA_M4U 5162#define CLK_INFRA_MD1MCU 6163#define CLK_INFRA_MD1BUS 7164#define CLK_INFRA_MD1DBB 8165#define CLK_INFRA_DEVICE_APC 9166#define CLK_INFRA_TRNG 10167#define CLK_INFRA_MD1LTE 11168#define CLK_INFRA_CPUM 12169#define CLK_INFRA_KP 13170#define CLK_INFRA_CA53_C0_SEL 14171#define CLK_INFRA_CA53_C1_SEL 15172#define CLK_INFRA_NR_CLK 16173 174/* PERI_SYS */175#define CLK_PERI_NFI 0176#define CLK_PERI_THERM 1177#define CLK_PERI_PWM1 2178#define CLK_PERI_PWM2 3179#define CLK_PERI_PWM3 4180#define CLK_PERI_PWM4 5181#define CLK_PERI_PWM5 6182#define CLK_PERI_PWM6 7183#define CLK_PERI_PWM7 8184#define CLK_PERI_PWM 9185#define CLK_PERI_USB0 10186#define CLK_PERI_USB1 11187#define CLK_PERI_AP_DMA 12188#define CLK_PERI_MSDC30_0 13189#define CLK_PERI_MSDC30_1 14190#define CLK_PERI_MSDC30_2 15191#define CLK_PERI_MSDC30_3 16192#define CLK_PERI_NLI_ARB 17193#define CLK_PERI_IRDA 18194#define CLK_PERI_UART0 19195#define CLK_PERI_UART1 20196#define CLK_PERI_UART2 21197#define CLK_PERI_UART3 22198#define CLK_PERI_I2C0 23199#define CLK_PERI_I2C1 24200#define CLK_PERI_I2C2 25201#define CLK_PERI_I2C3 26202#define CLK_PERI_I2C4 27203#define CLK_PERI_AUXADC 28204#define CLK_PERI_SPI0 29205#define CLK_PERI_UART0_SEL 30206#define CLK_PERI_UART1_SEL 31207#define CLK_PERI_UART2_SEL 32208#define CLK_PERI_UART3_SEL 33209#define CLK_PERI_NR_CLK 34210 211/* MFG */212#define CLK_MFG_BAXI 0213#define CLK_MFG_BMEM 1214#define CLK_MFG_BG3D 2215#define CLK_MFG_B26M 3216#define CLK_MFG_NR_CLK 4217 218/* MM_SYS */219#define CLK_MM_SMI_COMMON 0220#define CLK_MM_SMI_LARB0 1221#define CLK_MM_CAM_MDP 2222#define CLK_MM_MDP_RDMA0 3223#define CLK_MM_MDP_RDMA1 4224#define CLK_MM_MDP_RSZ0 5225#define CLK_MM_MDP_RSZ1 6226#define CLK_MM_MDP_RSZ2 7227#define CLK_MM_MDP_TDSHP0 8228#define CLK_MM_MDP_TDSHP1 9229#define CLK_MM_MDP_CROP 10230#define CLK_MM_MDP_WDMA 11231#define CLK_MM_MDP_WROT0 12232#define CLK_MM_MDP_WROT1 13233#define CLK_MM_FAKE_ENG 14234#define CLK_MM_MUTEX_32K 15235#define CLK_MM_DISP_OVL0 16236#define CLK_MM_DISP_OVL1 17237#define CLK_MM_DISP_RDMA0 18238#define CLK_MM_DISP_RDMA1 19239#define CLK_MM_DISP_RDMA2 20240#define CLK_MM_DISP_WDMA0 21241#define CLK_MM_DISP_WDMA1 22242#define CLK_MM_DISP_COLOR0 23243#define CLK_MM_DISP_COLOR1 24244#define CLK_MM_DISP_AAL 25245#define CLK_MM_DISP_GAMMA 26246#define CLK_MM_DISP_UFOE 27247#define CLK_MM_DISP_SPLIT0 28248#define CLK_MM_DISP_SPLIT1 29249#define CLK_MM_DISP_MERGE 30250#define CLK_MM_DISP_OD 31251#define CLK_MM_DISP_PWM0MM 32252#define CLK_MM_DISP_PWM026M 33253#define CLK_MM_DISP_PWM1MM 34254#define CLK_MM_DISP_PWM126M 35255#define CLK_MM_DSI0_ENGINE 36256#define CLK_MM_DSI0_DIGITAL 37257#define CLK_MM_DSI1_ENGINE 38258#define CLK_MM_DSI1_DIGITAL 39259#define CLK_MM_DPI_PIXEL 40260#define CLK_MM_DPI_ENGINE 41261#define CLK_MM_NR_CLK 42262 263/* VDEC_SYS */264#define CLK_VDEC_CKEN 0265#define CLK_VDEC_LARB_CKEN 1266#define CLK_VDEC_NR_CLK 2267 268/* VENC_SYS */269#define CLK_VENC_LARB 0270#define CLK_VENC_VENC 1271#define CLK_VENC_JPGENC 2272#define CLK_VENC_JPGDEC 3273#define CLK_VENC_NR_CLK 4274 275#endif /* _DT_BINDINGS_CLK_MT6795_H */276