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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (c) 2021 MediaTek Inc.4 * Author: Wenzhen.Yu <wenzhen.yu@mediatek.com>5 * Author: Jianhui Zhao <zhaojh329@gmail.com>6 * Author: Daniel Golle <daniel@makrotopia.org>7 */8 9#ifndef _DT_BINDINGS_CLK_MT7981_H10#define _DT_BINDINGS_CLK_MT7981_H11 12/* TOPCKGEN */13#define CLK_TOP_CB_CKSQ_40M 014#define CLK_TOP_CB_M_416M 115#define CLK_TOP_CB_M_D2 216#define CLK_TOP_CB_M_D3 317#define CLK_TOP_M_D3_D2 418#define CLK_TOP_CB_M_D4 519#define CLK_TOP_CB_M_D8 620#define CLK_TOP_M_D8_D2 721#define CLK_TOP_CB_MM_720M 822#define CLK_TOP_CB_MM_D2 923#define CLK_TOP_CB_MM_D3 1024#define CLK_TOP_CB_MM_D3_D5 1125#define CLK_TOP_CB_MM_D4 1226#define CLK_TOP_CB_MM_D6 1327#define CLK_TOP_MM_D6_D2 1428#define CLK_TOP_CB_MM_D8 1529#define CLK_TOP_CB_APLL2_196M 1630#define CLK_TOP_APLL2_D2 1731#define CLK_TOP_APLL2_D4 1832#define CLK_TOP_NET1_2500M 1933#define CLK_TOP_CB_NET1_D4 2034#define CLK_TOP_CB_NET1_D5 2135#define CLK_TOP_NET1_D5_D2 2236#define CLK_TOP_NET1_D5_D4 2337#define CLK_TOP_CB_NET1_D8 2438#define CLK_TOP_NET1_D8_D2 2539#define CLK_TOP_NET1_D8_D4 2640#define CLK_TOP_CB_NET2_800M 2741#define CLK_TOP_CB_NET2_D2 2842#define CLK_TOP_CB_NET2_D4 2943#define CLK_TOP_NET2_D4_D2 3044#define CLK_TOP_NET2_D4_D4 3145#define CLK_TOP_CB_NET2_D6 3246#define CLK_TOP_CB_WEDMCU_208M 3347#define CLK_TOP_CB_SGM_325M 3448#define CLK_TOP_CKSQ_40M_D2 3549#define CLK_TOP_CB_RTC_32K 3650#define CLK_TOP_CB_RTC_32P7K 3751#define CLK_TOP_USB_TX250M 3852#define CLK_TOP_FAUD 3953#define CLK_TOP_NFI1X 4054#define CLK_TOP_USB_EQ_RX250M 4155#define CLK_TOP_USB_CDR_CK 4256#define CLK_TOP_USB_LN0_CK 4357#define CLK_TOP_SPINFI_BCK 4458#define CLK_TOP_SPI 4559#define CLK_TOP_SPIM_MST 4660#define CLK_TOP_UART_BCK 4761#define CLK_TOP_PWM_BCK 4862#define CLK_TOP_I2C_BCK 4963#define CLK_TOP_PEXTP_TL 5064#define CLK_TOP_EMMC_208M 5165#define CLK_TOP_EMMC_400M 5266#define CLK_TOP_DRAMC_REF 5367#define CLK_TOP_DRAMC_MD32 5468#define CLK_TOP_SYSAXI 5569#define CLK_TOP_SYSAPB 5670#define CLK_TOP_ARM_DB_MAIN 5771#define CLK_TOP_AP2CNN_HOST 5872#define CLK_TOP_NETSYS 5973#define CLK_TOP_NETSYS_500M 6074#define CLK_TOP_NETSYS_WED_MCU 6175#define CLK_TOP_NETSYS_2X 6276#define CLK_TOP_SGM_325M 6377#define CLK_TOP_SGM_REG 6478#define CLK_TOP_F26M 6579#define CLK_TOP_EIP97B 6680#define CLK_TOP_USB3_PHY 6781#define CLK_TOP_AUD 6882#define CLK_TOP_A1SYS 6983#define CLK_TOP_AUD_L 7084#define CLK_TOP_A_TUNER 7185#define CLK_TOP_U2U3_REF 7286#define CLK_TOP_U2U3_SYS 7387#define CLK_TOP_U2U3_XHCI 7488#define CLK_TOP_USB_FRMCNT 7589#define CLK_TOP_NFI1X_SEL 7690#define CLK_TOP_SPINFI_SEL 7791#define CLK_TOP_SPI_SEL 7892#define CLK_TOP_SPIM_MST_SEL 7993#define CLK_TOP_UART_SEL 8094#define CLK_TOP_PWM_SEL 8195#define CLK_TOP_I2C_SEL 8296#define CLK_TOP_PEXTP_TL_SEL 8397#define CLK_TOP_EMMC_208M_SEL 8498#define CLK_TOP_EMMC_400M_SEL 8599#define CLK_TOP_F26M_SEL 86100#define CLK_TOP_DRAMC_SEL 87101#define CLK_TOP_DRAMC_MD32_SEL 88102#define CLK_TOP_SYSAXI_SEL 89103#define CLK_TOP_SYSAPB_SEL 90104#define CLK_TOP_ARM_DB_MAIN_SEL 91105#define CLK_TOP_AP2CNN_HOST_SEL 92106#define CLK_TOP_NETSYS_SEL 93107#define CLK_TOP_NETSYS_500M_SEL 94108#define CLK_TOP_NETSYS_MCU_SEL 95109#define CLK_TOP_NETSYS_2X_SEL 96110#define CLK_TOP_SGM_325M_SEL 97111#define CLK_TOP_SGM_REG_SEL 98112#define CLK_TOP_EIP97B_SEL 99113#define CLK_TOP_USB3_PHY_SEL 100114#define CLK_TOP_AUD_SEL 101115#define CLK_TOP_A1SYS_SEL 102116#define CLK_TOP_AUD_L_SEL 103117#define CLK_TOP_A_TUNER_SEL 104118#define CLK_TOP_U2U3_SEL 105119#define CLK_TOP_U2U3_SYS_SEL 106120#define CLK_TOP_U2U3_XHCI_SEL 107121#define CLK_TOP_USB_FRMCNT_SEL 108122#define CLK_TOP_AUD_I2S_M 109123 124/* INFRACFG */125#define CLK_INFRA_66M_MCK 0126#define CLK_INFRA_UART0_SEL 1127#define CLK_INFRA_UART1_SEL 2128#define CLK_INFRA_UART2_SEL 3129#define CLK_INFRA_SPI0_SEL 4130#define CLK_INFRA_SPI1_SEL 5131#define CLK_INFRA_SPI2_SEL 6132#define CLK_INFRA_PWM1_SEL 7133#define CLK_INFRA_PWM2_SEL 8134#define CLK_INFRA_PWM3_SEL 9135#define CLK_INFRA_PWM_BSEL 10136#define CLK_INFRA_PCIE_SEL 11137#define CLK_INFRA_GPT_STA 12138#define CLK_INFRA_PWM_HCK 13139#define CLK_INFRA_PWM_STA 14140#define CLK_INFRA_PWM1_CK 15141#define CLK_INFRA_PWM2_CK 16142#define CLK_INFRA_PWM3_CK 17143#define CLK_INFRA_CQ_DMA_CK 18144#define CLK_INFRA_AUD_BUS_CK 19145#define CLK_INFRA_AUD_26M_CK 20146#define CLK_INFRA_AUD_L_CK 21147#define CLK_INFRA_AUD_AUD_CK 22148#define CLK_INFRA_AUD_EG2_CK 23149#define CLK_INFRA_DRAMC_26M_CK 24150#define CLK_INFRA_DBG_CK 25151#define CLK_INFRA_AP_DMA_CK 26152#define CLK_INFRA_SEJ_CK 27153#define CLK_INFRA_SEJ_13M_CK 28154#define CLK_INFRA_THERM_CK 29155#define CLK_INFRA_I2C0_CK 30156#define CLK_INFRA_UART0_CK 31157#define CLK_INFRA_UART1_CK 32158#define CLK_INFRA_UART2_CK 33159#define CLK_INFRA_SPI2_CK 34160#define CLK_INFRA_SPI2_HCK_CK 35161#define CLK_INFRA_NFI1_CK 36162#define CLK_INFRA_SPINFI1_CK 37163#define CLK_INFRA_NFI_HCK_CK 38164#define CLK_INFRA_SPI0_CK 39165#define CLK_INFRA_SPI1_CK 40166#define CLK_INFRA_SPI0_HCK_CK 41167#define CLK_INFRA_SPI1_HCK_CK 42168#define CLK_INFRA_FRTC_CK 43169#define CLK_INFRA_MSDC_CK 44170#define CLK_INFRA_MSDC_HCK_CK 45171#define CLK_INFRA_MSDC_133M_CK 46172#define CLK_INFRA_MSDC_66M_CK 47173#define CLK_INFRA_ADC_26M_CK 48174#define CLK_INFRA_ADC_FRC_CK 49175#define CLK_INFRA_FBIST2FPC_CK 50176#define CLK_INFRA_I2C_MCK_CK 51177#define CLK_INFRA_I2C_PCK_CK 52178#define CLK_INFRA_IUSB_133_CK 53179#define CLK_INFRA_IUSB_66M_CK 54180#define CLK_INFRA_IUSB_SYS_CK 55181#define CLK_INFRA_IUSB_CK 56182#define CLK_INFRA_IPCIE_CK 57183#define CLK_INFRA_IPCIE_PIPE_CK 58184#define CLK_INFRA_IPCIER_CK 59185#define CLK_INFRA_IPCIEB_CK 60186 187/* APMIXEDSYS */188#define CLK_APMIXED_ARMPLL 0189#define CLK_APMIXED_NET2PLL 1190#define CLK_APMIXED_MMPLL 2191#define CLK_APMIXED_SGMPLL 3192#define CLK_APMIXED_WEDMCUPLL 4193#define CLK_APMIXED_NET1PLL 5194#define CLK_APMIXED_MPLL 6195#define CLK_APMIXED_APLL2 7196 197/* SGMIISYS_0 */198#define CLK_SGM0_TX_EN 0199#define CLK_SGM0_RX_EN 1200#define CLK_SGM0_CK0_EN 2201#define CLK_SGM0_CDR_CK0_EN 3202 203/* SGMIISYS_1 */204#define CLK_SGM1_TX_EN 0205#define CLK_SGM1_RX_EN 1206#define CLK_SGM1_CK1_EN 2207#define CLK_SGM1_CDR_CK1_EN 3208 209/* ETHSYS */210#define CLK_ETH_FE_EN 0211#define CLK_ETH_GP2_EN 1212#define CLK_ETH_GP1_EN 2213#define CLK_ETH_WOCPU0_EN 3214 215#endif /* _DT_BINDINGS_CLK_MT7981_H */216