281 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (c) 2023 MediaTek Inc.4 * Author: Sam Shih <sam.shih@mediatek.com>5 * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>6 */7 8#ifndef _DT_BINDINGS_CLK_MT7988_H9#define _DT_BINDINGS_CLK_MT7988_H10 11/* APMIXEDSYS */12 13#define CLK_APMIXED_NETSYSPLL 014#define CLK_APMIXED_MPLL 115#define CLK_APMIXED_MMPLL 216#define CLK_APMIXED_APLL2 317#define CLK_APMIXED_NET1PLL 418#define CLK_APMIXED_NET2PLL 519#define CLK_APMIXED_WEDMCUPLL 620#define CLK_APMIXED_SGMPLL 721#define CLK_APMIXED_ARM_B 822#define CLK_APMIXED_CCIPLL2_B 923#define CLK_APMIXED_USXGMIIPLL 1024#define CLK_APMIXED_MSDCPLL 1125 26/* TOPCKGEN */27 28#define CLK_TOP_XTAL 029#define CLK_TOP_XTAL_D2 130#define CLK_TOP_RTC_32K 231#define CLK_TOP_RTC_32P7K 332#define CLK_TOP_MPLL_D2 433#define CLK_TOP_MPLL_D3_D2 534#define CLK_TOP_MPLL_D4 635#define CLK_TOP_MPLL_D8 736#define CLK_TOP_MPLL_D8_D2 837#define CLK_TOP_MMPLL_D2 938#define CLK_TOP_MMPLL_D3_D5 1039#define CLK_TOP_MMPLL_D4 1140#define CLK_TOP_MMPLL_D6_D2 1241#define CLK_TOP_MMPLL_D8 1342#define CLK_TOP_APLL2_D4 1443#define CLK_TOP_NET1PLL_D4 1544#define CLK_TOP_NET1PLL_D5 1645#define CLK_TOP_NET1PLL_D5_D2 1746#define CLK_TOP_NET1PLL_D5_D4 1847#define CLK_TOP_NET1PLL_D8 1948#define CLK_TOP_NET1PLL_D8_D2 2049#define CLK_TOP_NET1PLL_D8_D4 2150#define CLK_TOP_NET1PLL_D8_D8 2251#define CLK_TOP_NET1PLL_D8_D16 2352#define CLK_TOP_NET2PLL_D2 2453#define CLK_TOP_NET2PLL_D4 2554#define CLK_TOP_NET2PLL_D4_D4 2655#define CLK_TOP_NET2PLL_D4_D8 2756#define CLK_TOP_NET2PLL_D6 2857#define CLK_TOP_NET2PLL_D8 2958#define CLK_TOP_NETSYS_SEL 3059#define CLK_TOP_NETSYS_500M_SEL 3160#define CLK_TOP_NETSYS_2X_SEL 3261#define CLK_TOP_NETSYS_GSW_SEL 3362#define CLK_TOP_ETH_GMII_SEL 3463#define CLK_TOP_NETSYS_MCU_SEL 3564#define CLK_TOP_NETSYS_PAO_2X_SEL 3665#define CLK_TOP_EIP197_SEL 3766#define CLK_TOP_AXI_INFRA_SEL 3867#define CLK_TOP_UART_SEL 3968#define CLK_TOP_EMMC_250M_SEL 4069#define CLK_TOP_EMMC_400M_SEL 4170#define CLK_TOP_SPI_SEL 4271#define CLK_TOP_SPIM_MST_SEL 4372#define CLK_TOP_NFI1X_SEL 4473#define CLK_TOP_SPINFI_SEL 4574#define CLK_TOP_PWM_SEL 4675#define CLK_TOP_I2C_SEL 4776#define CLK_TOP_PCIE_MBIST_250M_SEL 4877#define CLK_TOP_PEXTP_TL_SEL 4978#define CLK_TOP_PEXTP_TL_P1_SEL 5079#define CLK_TOP_PEXTP_TL_P2_SEL 5180#define CLK_TOP_PEXTP_TL_P3_SEL 5281#define CLK_TOP_USB_SYS_SEL 5382#define CLK_TOP_USB_SYS_P1_SEL 5483#define CLK_TOP_USB_XHCI_SEL 5584#define CLK_TOP_USB_XHCI_P1_SEL 5685#define CLK_TOP_USB_FRMCNT_SEL 5786#define CLK_TOP_USB_FRMCNT_P1_SEL 5887#define CLK_TOP_AUD_SEL 5988#define CLK_TOP_A1SYS_SEL 6089#define CLK_TOP_AUD_L_SEL 6190#define CLK_TOP_A_TUNER_SEL 6291#define CLK_TOP_SSPXTP_SEL 6392#define CLK_TOP_USB_PHY_SEL 6493#define CLK_TOP_USXGMII_SBUS_0_SEL 6594#define CLK_TOP_USXGMII_SBUS_1_SEL 6695#define CLK_TOP_SGM_0_SEL 6796#define CLK_TOP_SGM_SBUS_0_SEL 6897#define CLK_TOP_SGM_1_SEL 6998#define CLK_TOP_SGM_SBUS_1_SEL 7099#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71100#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72101#define CLK_TOP_SYSAXI_SEL 73102#define CLK_TOP_SYSAPB_SEL 74103#define CLK_TOP_ETH_REFCK_50M_SEL 75104#define CLK_TOP_ETH_SYS_200M_SEL 76105#define CLK_TOP_ETH_SYS_SEL 77106#define CLK_TOP_ETH_XGMII_SEL 78107#define CLK_TOP_BUS_TOPS_SEL 79108#define CLK_TOP_NPU_TOPS_SEL 80109#define CLK_TOP_DRAMC_SEL 81110#define CLK_TOP_DRAMC_MD32_SEL 82111#define CLK_TOP_INFRA_F26M_SEL 83112#define CLK_TOP_PEXTP_P0_SEL 84113#define CLK_TOP_PEXTP_P1_SEL 85114#define CLK_TOP_PEXTP_P2_SEL 86115#define CLK_TOP_PEXTP_P3_SEL 87116#define CLK_TOP_DA_XTP_GLB_P0_SEL 88117#define CLK_TOP_DA_XTP_GLB_P1_SEL 89118#define CLK_TOP_DA_XTP_GLB_P2_SEL 90119#define CLK_TOP_DA_XTP_GLB_P3_SEL 91120#define CLK_TOP_CKM_SEL 92121#define CLK_TOP_DA_SEL 93122#define CLK_TOP_PEXTP_SEL 94123#define CLK_TOP_TOPS_P2_26M_SEL 95124#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96125#define CLK_TOP_NETSYS_SYNC_250M_SEL 97126#define CLK_TOP_MACSEC_SEL 98127#define CLK_TOP_NETSYS_TOPS_400M_SEL 99128#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100129#define CLK_TOP_NETSYS_WARP_SEL 101130#define CLK_TOP_ETH_MII_SEL 102131#define CLK_TOP_NPU_SEL 103132#define CLK_TOP_AUD_I2S_M 104133 134/* MCUSYS */135 136#define CLK_MCU_BUS_DIV_SEL 0137#define CLK_MCU_ARM_DIV_SEL 1138 139/* INFRACFG_AO */140 141#define CLK_INFRA_MUX_UART0_SEL 0142#define CLK_INFRA_MUX_UART1_SEL 1143#define CLK_INFRA_MUX_UART2_SEL 2144#define CLK_INFRA_MUX_SPI0_SEL 3145#define CLK_INFRA_MUX_SPI1_SEL 4146#define CLK_INFRA_MUX_SPI2_SEL 5147#define CLK_INFRA_PWM_SEL 6148#define CLK_INFRA_PWM_CK1_SEL 7149#define CLK_INFRA_PWM_CK2_SEL 8150#define CLK_INFRA_PWM_CK3_SEL 9151#define CLK_INFRA_PWM_CK4_SEL 10152#define CLK_INFRA_PWM_CK5_SEL 11153#define CLK_INFRA_PWM_CK6_SEL 12154#define CLK_INFRA_PWM_CK7_SEL 13155#define CLK_INFRA_PWM_CK8_SEL 14156#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15157#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16158#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17159#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18160 161/* INFRACFG */162 163#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19164#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20165#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21166#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22167#define CLK_INFRA_66M_GPT_BCK 23168#define CLK_INFRA_66M_PWM_HCK 24169#define CLK_INFRA_66M_PWM_BCK 25170#define CLK_INFRA_66M_PWM_CK1 26171#define CLK_INFRA_66M_PWM_CK2 27172#define CLK_INFRA_66M_PWM_CK3 28173#define CLK_INFRA_66M_PWM_CK4 29174#define CLK_INFRA_66M_PWM_CK5 30175#define CLK_INFRA_66M_PWM_CK6 31176#define CLK_INFRA_66M_PWM_CK7 32177#define CLK_INFRA_66M_PWM_CK8 33178#define CLK_INFRA_133M_CQDMA_BCK 34179#define CLK_INFRA_66M_AUD_SLV_BCK 35180#define CLK_INFRA_AUD_26M 36181#define CLK_INFRA_AUD_L 37182#define CLK_INFRA_AUD_AUD 38183#define CLK_INFRA_AUD_EG2 39184#define CLK_INFRA_DRAMC_F26M 40185#define CLK_INFRA_133M_DBG_ACKM 41186#define CLK_INFRA_66M_AP_DMA_BCK 42187#define CLK_INFRA_66M_SEJ_BCK 43188#define CLK_INFRA_PRE_CK_SEJ_F13M 44189#define CLK_INFRA_26M_THERM_SYSTEM 45190#define CLK_INFRA_I2C_BCK 46191#define CLK_INFRA_52M_UART0_CK 47192#define CLK_INFRA_52M_UART1_CK 48193#define CLK_INFRA_52M_UART2_CK 49194#define CLK_INFRA_NFI 50195#define CLK_INFRA_SPINFI 51196#define CLK_INFRA_66M_NFI_HCK 52197#define CLK_INFRA_104M_SPI0 53198#define CLK_INFRA_104M_SPI1 54199#define CLK_INFRA_104M_SPI2_BCK 55200#define CLK_INFRA_66M_SPI0_HCK 56201#define CLK_INFRA_66M_SPI1_HCK 57202#define CLK_INFRA_66M_SPI2_HCK 58203#define CLK_INFRA_66M_FLASHIF_AXI 59204#define CLK_INFRA_RTC 60205#define CLK_INFRA_26M_ADC_BCK 61206#define CLK_INFRA_RC_ADC 62207#define CLK_INFRA_MSDC400 63208#define CLK_INFRA_MSDC2_HCK 64209#define CLK_INFRA_133M_MSDC_0_HCK 65210#define CLK_INFRA_66M_MSDC_0_HCK 66211#define CLK_INFRA_133M_CPUM_BCK 67212#define CLK_INFRA_BIST2FPC 68213#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69214#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70215#define CLK_INFRA_133M_USB_HCK 71216#define CLK_INFRA_133M_USB_HCK_CK_P1 72217#define CLK_INFRA_66M_USB_HCK 73218#define CLK_INFRA_66M_USB_HCK_CK_P1 74219#define CLK_INFRA_USB_SYS 75220#define CLK_INFRA_USB_SYS_CK_P1 76221#define CLK_INFRA_USB_REF 77222#define CLK_INFRA_USB_CK_P1 78223#define CLK_INFRA_USB_FRMCNT 79224#define CLK_INFRA_USB_FRMCNT_CK_P1 80225#define CLK_INFRA_USB_PIPE 81226#define CLK_INFRA_USB_PIPE_CK_P1 82227#define CLK_INFRA_USB_UTMI 83228#define CLK_INFRA_USB_UTMI_CK_P1 84229#define CLK_INFRA_USB_XHCI 85230#define CLK_INFRA_USB_XHCI_CK_P1 86231#define CLK_INFRA_PCIE_GFMUX_TL_P0 87232#define CLK_INFRA_PCIE_GFMUX_TL_P1 88233#define CLK_INFRA_PCIE_GFMUX_TL_P2 89234#define CLK_INFRA_PCIE_GFMUX_TL_P3 90235#define CLK_INFRA_PCIE_PIPE_P0 91236#define CLK_INFRA_PCIE_PIPE_P1 92237#define CLK_INFRA_PCIE_PIPE_P2 93238#define CLK_INFRA_PCIE_PIPE_P3 94239#define CLK_INFRA_133M_PCIE_CK_P0 95240#define CLK_INFRA_133M_PCIE_CK_P1 96241#define CLK_INFRA_133M_PCIE_CK_P2 97242#define CLK_INFRA_133M_PCIE_CK_P3 98243 244/* ETHDMA */245 246#define CLK_ETHDMA_XGP1_EN 0247#define CLK_ETHDMA_XGP2_EN 1248#define CLK_ETHDMA_XGP3_EN 2249#define CLK_ETHDMA_FE_EN 3250#define CLK_ETHDMA_GP2_EN 4251#define CLK_ETHDMA_GP1_EN 5252#define CLK_ETHDMA_GP3_EN 6253#define CLK_ETHDMA_ESW_EN 7254#define CLK_ETHDMA_CRYPT0_EN 8255#define CLK_ETHDMA_NR_CLK 9256 257/* SGMIISYS_0 */258 259#define CLK_SGM0_TX_EN 0260#define CLK_SGM0_RX_EN 1261#define CLK_SGMII0_NR_CLK 2262 263/* SGMIISYS_1 */264 265#define CLK_SGM1_TX_EN 0266#define CLK_SGM1_RX_EN 1267#define CLK_SGMII1_NR_CLK 2268 269/* ETHWARP */270 271#define CLK_ETHWARP_WOCPU2_EN 0272#define CLK_ETHWARP_WOCPU1_EN 1273#define CLK_ETHWARP_WOCPU0_EN 2274#define CLK_ETHWARP_NR_CLK 3275 276/* XFIPLL */277#define CLK_XFIPLL_PLL 0278#define CLK_XFIPLL_PLL_EN 1279 280#endif /* _DT_BINDINGS_CLK_MT7988_H */281