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1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */2/*3 * Copyright (c) 2022 MediaTek Inc.4 * Author: Garmin Chang <garmin.chang@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_CLK_MT8188_H8#define _DT_BINDINGS_CLK_MT8188_H9 10/* TOPCKGEN */11#define CLK_TOP_AXI 012#define CLK_TOP_SPM 113#define CLK_TOP_SCP 214#define CLK_TOP_BUS_AXIMEM 315#define CLK_TOP_VPP 416#define CLK_TOP_ETHDR 517#define CLK_TOP_IPE 618#define CLK_TOP_CAM 719#define CLK_TOP_CCU 820#define CLK_TOP_CCU_AHB 921#define CLK_TOP_IMG 1022#define CLK_TOP_CAMTM 1123#define CLK_TOP_DSP 1224#define CLK_TOP_DSP1 1325#define CLK_TOP_DSP2 1426#define CLK_TOP_DSP3 1527#define CLK_TOP_DSP4 1628#define CLK_TOP_DSP5 1729#define CLK_TOP_DSP6 1830#define CLK_TOP_DSP7 1931#define CLK_TOP_MFG_CORE_TMP 2032#define CLK_TOP_CAMTG 2133#define CLK_TOP_CAMTG2 2234#define CLK_TOP_CAMTG3 2335#define CLK_TOP_UART 2436#define CLK_TOP_SPI 2537#define CLK_TOP_MSDC50_0_HCLK 2638#define CLK_TOP_MSDC50_0 2739#define CLK_TOP_MSDC30_1 2840#define CLK_TOP_MSDC30_2 2941#define CLK_TOP_INTDIR 3042#define CLK_TOP_AUD_INTBUS 3143#define CLK_TOP_AUDIO_H 3244#define CLK_TOP_PWRAP_ULPOSC 3345#define CLK_TOP_ATB 3446#define CLK_TOP_SSPM 3547#define CLK_TOP_DP 3648#define CLK_TOP_EDP 3749#define CLK_TOP_DPI 3850#define CLK_TOP_DISP_PWM0 3951#define CLK_TOP_DISP_PWM1 4052#define CLK_TOP_USB_TOP 4153#define CLK_TOP_SSUSB_XHCI 4254#define CLK_TOP_USB_TOP_2P 4355#define CLK_TOP_SSUSB_XHCI_2P 4456#define CLK_TOP_USB_TOP_3P 4557#define CLK_TOP_SSUSB_XHCI_3P 4658#define CLK_TOP_I2C 4759#define CLK_TOP_SENINF 4860#define CLK_TOP_SENINF1 4961#define CLK_TOP_GCPU 5062#define CLK_TOP_VENC 5163#define CLK_TOP_VDEC 5264#define CLK_TOP_PWM 5365#define CLK_TOP_MCUPM 5466#define CLK_TOP_SPMI_P_MST 5567#define CLK_TOP_SPMI_M_MST 5668#define CLK_TOP_DVFSRC 5769#define CLK_TOP_TL 5870#define CLK_TOP_AES_MSDCFDE 5971#define CLK_TOP_DSI_OCC 6072#define CLK_TOP_WPE_VPP 6173#define CLK_TOP_HDCP 6274#define CLK_TOP_HDCP_24M 6375#define CLK_TOP_HDMI_APB 6476#define CLK_TOP_SNPS_ETH_250M 6577#define CLK_TOP_SNPS_ETH_62P4M_PTP 6678#define CLK_TOP_SNPS_ETH_50M_RMII 6779#define CLK_TOP_ADSP 6880#define CLK_TOP_AUDIO_LOCAL_BUS 6981#define CLK_TOP_ASM_H 7082#define CLK_TOP_ASM_L 7183#define CLK_TOP_APLL1 7284#define CLK_TOP_APLL2 7385#define CLK_TOP_APLL3 7486#define CLK_TOP_APLL4 7587#define CLK_TOP_APLL5 7688#define CLK_TOP_I2SO1 7789#define CLK_TOP_I2SO2 7890#define CLK_TOP_I2SI1 7991#define CLK_TOP_I2SI2 8092#define CLK_TOP_DPTX 8193#define CLK_TOP_AUD_IEC 8294#define CLK_TOP_A1SYS_HP 8395#define CLK_TOP_A2SYS 8496#define CLK_TOP_A3SYS 8597#define CLK_TOP_A4SYS 8698#define CLK_TOP_ECC 8799#define CLK_TOP_SPINOR 88100#define CLK_TOP_ULPOSC 89101#define CLK_TOP_SRCK 90102#define CLK_TOP_MFG_CK_FAST_REF 91103#define CLK_TOP_MAINPLL_D3 92104#define CLK_TOP_MAINPLL_D4 93105#define CLK_TOP_MAINPLL_D4_D2 94106#define CLK_TOP_MAINPLL_D4_D4 95107#define CLK_TOP_MAINPLL_D4_D8 96108#define CLK_TOP_MAINPLL_D5 97109#define CLK_TOP_MAINPLL_D5_D2 98110#define CLK_TOP_MAINPLL_D5_D4 99111#define CLK_TOP_MAINPLL_D5_D8 100112#define CLK_TOP_MAINPLL_D6 101113#define CLK_TOP_MAINPLL_D6_D2 102114#define CLK_TOP_MAINPLL_D6_D4 103115#define CLK_TOP_MAINPLL_D6_D8 104116#define CLK_TOP_MAINPLL_D7 105117#define CLK_TOP_MAINPLL_D7_D2 106118#define CLK_TOP_MAINPLL_D7_D4 107119#define CLK_TOP_MAINPLL_D7_D8 108120#define CLK_TOP_MAINPLL_D9 109121#define CLK_TOP_UNIVPLL_D2 110122#define CLK_TOP_UNIVPLL_D3 111123#define CLK_TOP_UNIVPLL_D4 112124#define CLK_TOP_UNIVPLL_D4_D2 113125#define CLK_TOP_UNIVPLL_D4_D4 114126#define CLK_TOP_UNIVPLL_D4_D8 115127#define CLK_TOP_UNIVPLL_D5 116128#define CLK_TOP_UNIVPLL_D5_D2 117129#define CLK_TOP_UNIVPLL_D5_D4 118130#define CLK_TOP_UNIVPLL_D5_D8 119131#define CLK_TOP_UNIVPLL_D6 120132#define CLK_TOP_UNIVPLL_D6_D2 121133#define CLK_TOP_UNIVPLL_D6_D4 122134#define CLK_TOP_UNIVPLL_D6_D8 123135#define CLK_TOP_UNIVPLL_D7 124136#define CLK_TOP_UNIVPLL_192M 125137#define CLK_TOP_UNIVPLL_192M_D4 126138#define CLK_TOP_UNIVPLL_192M_D8 127139#define CLK_TOP_UNIVPLL_192M_D10 128140#define CLK_TOP_UNIVPLL_192M_D16 129141#define CLK_TOP_UNIVPLL_192M_D32 130142#define CLK_TOP_APLL1_D3 131143#define CLK_TOP_APLL1_D4 132144#define CLK_TOP_APLL2_D3 133145#define CLK_TOP_APLL2_D4 134146#define CLK_TOP_APLL3_D4 135147#define CLK_TOP_APLL4_D4 136148#define CLK_TOP_APLL5_D4 137149#define CLK_TOP_MMPLL_D4 138150#define CLK_TOP_MMPLL_D4_D2 139151#define CLK_TOP_MMPLL_D5 140152#define CLK_TOP_MMPLL_D5_D2 141153#define CLK_TOP_MMPLL_D5_D4 142154#define CLK_TOP_MMPLL_D6 143155#define CLK_TOP_MMPLL_D6_D2 144156#define CLK_TOP_MMPLL_D7 145157#define CLK_TOP_MMPLL_D9 146158#define CLK_TOP_TVDPLL1 147159#define CLK_TOP_TVDPLL1_D2 148160#define CLK_TOP_TVDPLL1_D4 149161#define CLK_TOP_TVDPLL1_D8 150162#define CLK_TOP_TVDPLL1_D16 151163#define CLK_TOP_TVDPLL2 152164#define CLK_TOP_TVDPLL2_D2 153165#define CLK_TOP_TVDPLL2_D4 154166#define CLK_TOP_TVDPLL2_D8 155167#define CLK_TOP_TVDPLL2_D16 156168#define CLK_TOP_MSDCPLL_D2 157169#define CLK_TOP_MSDCPLL_D16 158170#define CLK_TOP_ETHPLL 159171#define CLK_TOP_ETHPLL_D2 160172#define CLK_TOP_ETHPLL_D4 161173#define CLK_TOP_ETHPLL_D8 162174#define CLK_TOP_ETHPLL_D10 163175#define CLK_TOP_ADSPPLL_D2 164176#define CLK_TOP_ADSPPLL_D4 165177#define CLK_TOP_ADSPPLL_D8 166178#define CLK_TOP_ULPOSC1 167179#define CLK_TOP_ULPOSC1_D2 168180#define CLK_TOP_ULPOSC1_D4 169181#define CLK_TOP_ULPOSC1_D8 170182#define CLK_TOP_ULPOSC1_D7 171183#define CLK_TOP_ULPOSC1_D10 172184#define CLK_TOP_ULPOSC1_D16 173185#define CLK_TOP_MPHONE_SLAVE_BCK 174186#define CLK_TOP_PAD_FPC 175187#define CLK_TOP_466M_FMEM 176188#define CLK_TOP_PEXTP_PIPE 177189#define CLK_TOP_DSI_PHY 178190#define CLK_TOP_APLL12_CK_DIV0 179191#define CLK_TOP_APLL12_CK_DIV1 180192#define CLK_TOP_APLL12_CK_DIV2 181193#define CLK_TOP_APLL12_CK_DIV3 182194#define CLK_TOP_APLL12_CK_DIV4 183195#define CLK_TOP_APLL12_CK_DIV9 184196#define CLK_TOP_CFGREG_CLOCK_EN_VPP0 185197#define CLK_TOP_CFGREG_CLOCK_EN_VPP1 186198#define CLK_TOP_CFGREG_CLOCK_EN_VDO0 187199#define CLK_TOP_CFGREG_CLOCK_EN_VDO1 188200#define CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS 189201#define CLK_TOP_CFGREG_F26M_VPP0 190202#define CLK_TOP_CFGREG_F26M_VPP1 191203#define CLK_TOP_CFGREG_F26M_VDO0 192204#define CLK_TOP_CFGREG_F26M_VDO1 193205#define CLK_TOP_CFGREG_AUD_F26M_AUD 194206#define CLK_TOP_CFGREG_UNIPLL_SES 195207#define CLK_TOP_CFGREG_F_PCIE_PHY_REF 196208#define CLK_TOP_SSUSB_TOP_REF 197209#define CLK_TOP_SSUSB_PHY_REF 198210#define CLK_TOP_SSUSB_TOP_P1_REF 199211#define CLK_TOP_SSUSB_PHY_P1_REF 200212#define CLK_TOP_SSUSB_TOP_P2_REF 201213#define CLK_TOP_SSUSB_PHY_P2_REF 202214#define CLK_TOP_SSUSB_TOP_P3_REF 203215#define CLK_TOP_SSUSB_PHY_P3_REF 204216#define CLK_TOP_NR_CLK 205217 218/* INFRACFG_AO */219#define CLK_INFRA_AO_PMIC_TMR 0220#define CLK_INFRA_AO_PMIC_AP 1221#define CLK_INFRA_AO_PMIC_MD 2222#define CLK_INFRA_AO_PMIC_CONN 3223#define CLK_INFRA_AO_SEJ 4224#define CLK_INFRA_AO_APXGPT 5225#define CLK_INFRA_AO_GCE 6226#define CLK_INFRA_AO_GCE2 7227#define CLK_INFRA_AO_THERM 8228#define CLK_INFRA_AO_PWM_HCLK 9229#define CLK_INFRA_AO_PWM1 10230#define CLK_INFRA_AO_PWM2 11231#define CLK_INFRA_AO_PWM3 12232#define CLK_INFRA_AO_PWM4 13233#define CLK_INFRA_AO_PWM 14234#define CLK_INFRA_AO_UART0 15235#define CLK_INFRA_AO_UART1 16236#define CLK_INFRA_AO_UART2 17237#define CLK_INFRA_AO_UART3 18238#define CLK_INFRA_AO_UART4 19239#define CLK_INFRA_AO_GCE_26M 20240#define CLK_INFRA_AO_CQ_DMA_FPC 21241#define CLK_INFRA_AO_UART5 22242#define CLK_INFRA_AO_HDMI_26M 23243#define CLK_INFRA_AO_SPI0 24244#define CLK_INFRA_AO_MSDC0 25245#define CLK_INFRA_AO_MSDC1 26246#define CLK_INFRA_AO_MSDC2 27247#define CLK_INFRA_AO_MSDC0_SRC 28248#define CLK_INFRA_AO_DVFSRC 29249#define CLK_INFRA_AO_TRNG 30250#define CLK_INFRA_AO_AUXADC 31251#define CLK_INFRA_AO_CPUM 32252#define CLK_INFRA_AO_HDMI_32K 33253#define CLK_INFRA_AO_CEC_66M_HCLK 34254#define CLK_INFRA_AO_PCIE_TL_26M 35255#define CLK_INFRA_AO_MSDC1_SRC 36256#define CLK_INFRA_AO_CEC_66M_BCLK 37257#define CLK_INFRA_AO_PCIE_TL_96M 38258#define CLK_INFRA_AO_DEVICE_APC 39259#define CLK_INFRA_AO_ECC_66M_HCLK 40260#define CLK_INFRA_AO_DEBUGSYS 41261#define CLK_INFRA_AO_AUDIO 42262#define CLK_INFRA_AO_PCIE_TL_32K 43263#define CLK_INFRA_AO_DBG_TRACE 44264#define CLK_INFRA_AO_DRAMC_F26M 45265#define CLK_INFRA_AO_IRTX 46266#define CLK_INFRA_AO_DISP_PWM 47267#define CLK_INFRA_AO_CLDMA_BCLK 48268#define CLK_INFRA_AO_AUDIO_26M_BCLK 49269#define CLK_INFRA_AO_SPI1 50270#define CLK_INFRA_AO_SPI2 51271#define CLK_INFRA_AO_SPI3 52272#define CLK_INFRA_AO_FSSPM 53273#define CLK_INFRA_AO_SSPM_BUS_HCLK 54274#define CLK_INFRA_AO_APDMA_BCLK 55275#define CLK_INFRA_AO_SPI4 56276#define CLK_INFRA_AO_SPI5 57277#define CLK_INFRA_AO_CQ_DMA 58278#define CLK_INFRA_AO_MSDC0_SELF 59279#define CLK_INFRA_AO_MSDC1_SELF 60280#define CLK_INFRA_AO_MSDC2_SELF 61281#define CLK_INFRA_AO_I2S_DMA 62282#define CLK_INFRA_AO_AP_MSDC0 63283#define CLK_INFRA_AO_MD_MSDC0 64284#define CLK_INFRA_AO_MSDC30_2 65285#define CLK_INFRA_AO_GCPU 66286#define CLK_INFRA_AO_PCIE_PERI_26M 67287#define CLK_INFRA_AO_GCPU_66M_BCLK 68288#define CLK_INFRA_AO_GCPU_133M_BCLK 69289#define CLK_INFRA_AO_DISP_PWM1 70290#define CLK_INFRA_AO_FBIST2FPC 71291#define CLK_INFRA_AO_DEVICE_APC_SYNC 72292#define CLK_INFRA_AO_PCIE_P1_PERI_26M 73293#define CLK_INFRA_AO_133M_MCLK_CK 74294#define CLK_INFRA_AO_66M_MCLK_CK 75295#define CLK_INFRA_AO_PCIE_PL_P_250M_P0 76296#define CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P 77297#define CLK_INFRA_AO_NR_CLK 78298 299/* APMIXEDSYS */300#define CLK_APMIXED_ETHPLL 0301#define CLK_APMIXED_MSDCPLL 1302#define CLK_APMIXED_TVDPLL1 2303#define CLK_APMIXED_TVDPLL2 3304#define CLK_APMIXED_MMPLL 4305#define CLK_APMIXED_MAINPLL 5306#define CLK_APMIXED_IMGPLL 6307#define CLK_APMIXED_UNIVPLL 7308#define CLK_APMIXED_ADSPPLL 8309#define CLK_APMIXED_APLL1 9310#define CLK_APMIXED_APLL2 10311#define CLK_APMIXED_APLL3 11312#define CLK_APMIXED_APLL4 12313#define CLK_APMIXED_APLL5 13314#define CLK_APMIXED_MFGPLL 14315#define CLK_APMIXED_PLL_SSUSB26M_EN 15316#define CLK_APMIXED_NR_CLK 16317 318/* AUDIODSP */319#define CLK_AUDIODSP_AUDIO26M 0320#define CLK_AUDIODSP_NR_CLK 1321 322/* PERICFG_AO */323#define CLK_PERI_AO_ETHERNET 0324#define CLK_PERI_AO_ETHERNET_BUS 1325#define CLK_PERI_AO_FLASHIF_BUS 2326#define CLK_PERI_AO_FLASHIF_26M 3327#define CLK_PERI_AO_FLASHIFLASHCK 4328#define CLK_PERI_AO_SSUSB_2P_BUS 5329#define CLK_PERI_AO_SSUSB_2P_XHCI 6330#define CLK_PERI_AO_SSUSB_3P_BUS 7331#define CLK_PERI_AO_SSUSB_3P_XHCI 8332#define CLK_PERI_AO_SSUSB_BUS 9333#define CLK_PERI_AO_SSUSB_XHCI 10334#define CLK_PERI_AO_ETHERNET_MAC 11335#define CLK_PERI_AO_PCIE_P0_FMEM 12336#define CLK_PERI_AO_NR_CLK 13337 338/* IMP_IIC_WRAP_C */339#define CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0 0340#define CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2 1341#define CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3 2342#define CLK_IMP_IIC_WRAP_C_NR_CLK 3343 344/* IMP_IIC_WRAP_W */345#define CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1 0346#define CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4 1347#define CLK_IMP_IIC_WRAP_W_NR_CLK 2348 349/* IMP_IIC_WRAP_EN */350#define CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5 0351#define CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6 1352#define CLK_IMP_IIC_WRAP_EN_NR_CLK 2353 354/* MFGCFG */355#define CLK_MFGCFG_BG3D 0356#define CLK_MFGCFG_NR_CLK 1357 358/* VPPSYS0 */359#define CLK_VPP0_MDP_FG 0360#define CLK_VPP0_STITCH 1361#define CLK_VPP0_PADDING 2362#define CLK_VPP0_MDP_TCC 3363#define CLK_VPP0_WARP0_ASYNC_TX 4364#define CLK_VPP0_WARP1_ASYNC_TX 5365#define CLK_VPP0_MUTEX 6366#define CLK_VPP02VPP1_RELAY 7367#define CLK_VPP0_VPP12VPP0_ASYNC 8368#define CLK_VPP0_MMSYSRAM_TOP 9369#define CLK_VPP0_MDP_AAL 10370#define CLK_VPP0_MDP_RSZ 11371#define CLK_VPP0_SMI_COMMON_MMSRAM 12372#define CLK_VPP0_GALS_VDO0_LARB0_MMSRAM 13373#define CLK_VPP0_GALS_VDO0_LARB1_MMSRAM 14374#define CLK_VPP0_GALS_VENCSYS_MMSRAM 15375#define CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM 16376#define CLK_VPP0_GALS_INFRA_MMSRAM 17377#define CLK_VPP0_GALS_CAMSYS_MMSRAM 18378#define CLK_VPP0_GALS_VPP1_LARB5_MMSRAM 19379#define CLK_VPP0_GALS_VPP1_LARB6_MMSRAM 20380#define CLK_VPP0_SMI_REORDER_MMSRAM 21381#define CLK_VPP0_SMI_IOMMU 22382#define CLK_VPP0_GALS_IMGSYS_CAMSYS 23383#define CLK_VPP0_MDP_RDMA 24384#define CLK_VPP0_MDP_WROT 25385#define CLK_VPP0_GALS_EMI0_EMI1 26386#define CLK_VPP0_SMI_SUB_COMMON_REORDER 27387#define CLK_VPP0_SMI_RSI 28388#define CLK_VPP0_SMI_COMMON_LARB4 29389#define CLK_VPP0_GALS_VDEC_VDEC_CORE1 30390#define CLK_VPP0_GALS_VPP1_WPESYS 31391#define CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1 32392#define CLK_VPP0_FAKE_ENG 33393#define CLK_VPP0_MDP_HDR 34394#define CLK_VPP0_MDP_TDSHP 35395#define CLK_VPP0_MDP_COLOR 36396#define CLK_VPP0_MDP_OVL 37397#define CLK_VPP0_DSIP_RDMA 38398#define CLK_VPP0_DISP_WDMA 39399#define CLK_VPP0_MDP_HMS 40400#define CLK_VPP0_WARP0_RELAY 41401#define CLK_VPP0_WARP0_ASYNC 42402#define CLK_VPP0_WARP1_RELAY 43403#define CLK_VPP0_WARP1_ASYNC 44404#define CLK_VPP0_NR_CLK 45405 406/* WPESYS */407#define CLK_WPE_TOP_WPE_VPP0 0408#define CLK_WPE_TOP_SMI_LARB7 1409#define CLK_WPE_TOP_WPESYS_EVENT_TX 2410#define CLK_WPE_TOP_SMI_LARB7_PCLK_EN 3411#define CLK_WPE_TOP_NR_CLK 4412 413/* WPESYS_VPP0 */414#define CLK_WPE_VPP0_VECI 0415#define CLK_WPE_VPP0_VEC2I 1416#define CLK_WPE_VPP0_VEC3I 2417#define CLK_WPE_VPP0_WPEO 3418#define CLK_WPE_VPP0_MSKO 4419#define CLK_WPE_VPP0_VGEN 5420#define CLK_WPE_VPP0_EXT 6421#define CLK_WPE_VPP0_VFC 7422#define CLK_WPE_VPP0_CACH0_TOP 8423#define CLK_WPE_VPP0_CACH0_DMA 9424#define CLK_WPE_VPP0_CACH1_TOP 10425#define CLK_WPE_VPP0_CACH1_DMA 11426#define CLK_WPE_VPP0_CACH2_TOP 12427#define CLK_WPE_VPP0_CACH2_DMA 13428#define CLK_WPE_VPP0_CACH3_TOP 14429#define CLK_WPE_VPP0_CACH3_DMA 15430#define CLK_WPE_VPP0_PSP 16431#define CLK_WPE_VPP0_PSP2 17432#define CLK_WPE_VPP0_SYNC 18433#define CLK_WPE_VPP0_C24 19434#define CLK_WPE_VPP0_MDP_CROP 20435#define CLK_WPE_VPP0_ISP_CROP 21436#define CLK_WPE_VPP0_TOP 22437#define CLK_WPE_VPP0_NR_CLK 23438 439/* VPPSYS1 */440#define CLK_VPP1_SVPP1_MDP_OVL 0441#define CLK_VPP1_SVPP1_MDP_TCC 1442#define CLK_VPP1_SVPP1_MDP_WROT 2443#define CLK_VPP1_SVPP1_VPP_PAD 3444#define CLK_VPP1_SVPP2_MDP_WROT 4445#define CLK_VPP1_SVPP2_VPP_PAD 5446#define CLK_VPP1_SVPP3_MDP_WROT 6447#define CLK_VPP1_SVPP3_VPP_PAD 7448#define CLK_VPP1_SVPP1_MDP_RDMA 8449#define CLK_VPP1_SVPP1_MDP_FG 9450#define CLK_VPP1_SVPP2_MDP_RDMA 10451#define CLK_VPP1_SVPP2_MDP_FG 11452#define CLK_VPP1_SVPP3_MDP_RDMA 12453#define CLK_VPP1_SVPP3_MDP_FG 13454#define CLK_VPP1_VPP_SPLIT 14455#define CLK_VPP1_SVPP2_VDO0_DL_RELAY 15456#define CLK_VPP1_SVPP1_MDP_RSZ 16457#define CLK_VPP1_SVPP1_MDP_TDSHP 17458#define CLK_VPP1_SVPP1_MDP_COLOR 18459#define CLK_VPP1_SVPP3_VDO1_DL_RELAY 19460#define CLK_VPP1_SVPP2_MDP_RSZ 20461#define CLK_VPP1_SVPP2_VPP_MERGE 21462#define CLK_VPP1_SVPP2_MDP_TDSHP 22463#define CLK_VPP1_SVPP2_MDP_COLOR 23464#define CLK_VPP1_SVPP3_MDP_RSZ 24465#define CLK_VPP1_SVPP3_VPP_MERGE 25466#define CLK_VPP1_SVPP3_MDP_TDSHP 26467#define CLK_VPP1_SVPP3_MDP_COLOR 27468#define CLK_VPP1_GALS5 28469#define CLK_VPP1_GALS6 29470#define CLK_VPP1_LARB5 30471#define CLK_VPP1_LARB6 31472#define CLK_VPP1_SVPP1_MDP_HDR 32473#define CLK_VPP1_SVPP1_MDP_AAL 33474#define CLK_VPP1_SVPP2_MDP_HDR 34475#define CLK_VPP1_SVPP2_MDP_AAL 35476#define CLK_VPP1_SVPP3_MDP_HDR 36477#define CLK_VPP1_SVPP3_MDP_AAL 37478#define CLK_VPP1_DISP_MUTEX 38479#define CLK_VPP1_SVPP2_VDO1_DL_RELAY 39480#define CLK_VPP1_SVPP3_VDO0_DL_RELAY 40481#define CLK_VPP1_VPP0_DL_ASYNC 41482#define CLK_VPP1_VPP0_DL1_RELAY 42483#define CLK_VPP1_LARB5_FAKE_ENG 43484#define CLK_VPP1_LARB6_FAKE_ENG 44485#define CLK_VPP1_HDMI_META 45486#define CLK_VPP1_VPP_SPLIT_HDMI 46487#define CLK_VPP1_DGI_IN 47488#define CLK_VPP1_DGI_OUT 48489#define CLK_VPP1_VPP_SPLIT_DGI 49490#define CLK_VPP1_DL_CON_OCC 50491#define CLK_VPP1_VPP_SPLIT_26M 51492#define CLK_VPP1_NR_CLK 52493 494/* IMGSYS */495#define CLK_IMGSYS_MAIN_LARB9 0496#define CLK_IMGSYS_MAIN_TRAW0 1497#define CLK_IMGSYS_MAIN_TRAW1 2498#define CLK_IMGSYS_MAIN_VCORE_GALS 3499#define CLK_IMGSYS_MAIN_DIP0 4500#define CLK_IMGSYS_MAIN_WPE0 5501#define CLK_IMGSYS_MAIN_IPE 6502#define CLK_IMGSYS_MAIN_WPE1 7503#define CLK_IMGSYS_MAIN_WPE2 8504#define CLK_IMGSYS_MAIN_GALS 9505#define CLK_IMGSYS_MAIN_NR_CLK 10506 507/* IMGSYS1_DIP_TOP */508#define CLK_IMGSYS1_DIP_TOP_LARB10 0509#define CLK_IMGSYS1_DIP_TOP_DIP_TOP 1510#define CLK_IMGSYS1_DIP_TOP_NR_CLK 2511 512/* IMGSYS1_DIP_NR */513#define CLK_IMGSYS1_DIP_NR_LARB15 0514#define CLK_IMGSYS1_DIP_NR_DIP_NR 1515#define CLK_IMGSYS1_DIP_NR_NR_CLK 2516 517/* IMGSYS_WPE1 */518#define CLK_IMGSYS_WPE1_LARB11 0519#define CLK_IMGSYS_WPE1 1520#define CLK_IMGSYS_WPE1_NR_CLK 2521 522/* IPESYS */523#define CLK_IPE_DPE 0524#define CLK_IPE_FDVT 1525#define CLK_IPE_ME 2526#define CLK_IPESYS_TOP 3527#define CLK_IPE_SMI_LARB12 4528#define CLK_IPE_NR_CLK 5529 530/* IMGSYS_WPE2 */531#define CLK_IMGSYS_WPE2_LARB11 0532#define CLK_IMGSYS_WPE2 1533#define CLK_IMGSYS_WPE2_NR_CLK 2534 535/* IMGSYS_WPE3 */536#define CLK_IMGSYS_WPE3_LARB11 0537#define CLK_IMGSYS_WPE3 1538#define CLK_IMGSYS_WPE3_NR_CLK 2539 540/* CAMSYS */541#define CLK_CAM_MAIN_LARB13 0542#define CLK_CAM_MAIN_LARB14 1543#define CLK_CAM_MAIN_CAM 2544#define CLK_CAM_MAIN_CAM_SUBA 3545#define CLK_CAM_MAIN_CAM_SUBB 4546#define CLK_CAM_MAIN_CAMTG 5547#define CLK_CAM_MAIN_SENINF 6548#define CLK_CAM_MAIN_GCAMSVA 7549#define CLK_CAM_MAIN_GCAMSVB 8550#define CLK_CAM_MAIN_GCAMSVC 9551#define CLK_CAM_MAIN_GCAMSVD 10552#define CLK_CAM_MAIN_GCAMSVE 11553#define CLK_CAM_MAIN_GCAMSVF 12554#define CLK_CAM_MAIN_GCAMSVG 13555#define CLK_CAM_MAIN_GCAMSVH 14556#define CLK_CAM_MAIN_GCAMSVI 15557#define CLK_CAM_MAIN_GCAMSVJ 16558#define CLK_CAM_MAIN_CAMSV_TOP 17559#define CLK_CAM_MAIN_CAMSV_CQ_A 18560#define CLK_CAM_MAIN_CAMSV_CQ_B 19561#define CLK_CAM_MAIN_CAMSV_CQ_C 20562#define CLK_CAM_MAIN_FAKE_ENG 21563#define CLK_CAM_MAIN_CAM2MM0_GALS 22564#define CLK_CAM_MAIN_CAM2MM1_GALS 23565#define CLK_CAM_MAIN_CAM2SYS_GALS 24566#define CLK_CAM_MAIN_NR_CLK 25567 568/* CAMSYS_RAWA */569#define CLK_CAM_RAWA_LARBX 0570#define CLK_CAM_RAWA_CAM 1571#define CLK_CAM_RAWA_CAMTG 2572#define CLK_CAM_RAWA_NR_CLK 3573 574/* CAMSYS_YUVA */575#define CLK_CAM_YUVA_LARBX 0576#define CLK_CAM_YUVA_CAM 1577#define CLK_CAM_YUVA_CAMTG 2578#define CLK_CAM_YUVA_NR_CLK 3579 580/* CAMSYS_RAWB */581#define CLK_CAM_RAWB_LARBX 0582#define CLK_CAM_RAWB_CAM 1583#define CLK_CAM_RAWB_CAMTG 2584#define CLK_CAM_RAWB_NR_CLK 3585 586/* CAMSYS_YUVB */587#define CLK_CAM_YUVB_LARBX 0588#define CLK_CAM_YUVB_CAM 1589#define CLK_CAM_YUVB_CAMTG 2590#define CLK_CAM_YUVB_NR_CLK 3591 592/* CCUSYS */593#define CLK_CCU_LARB27 0594#define CLK_CCU_AHB 1595#define CLK_CCU_CCU0 2596#define CLK_CCU_NR_CLK 3597 598/* VDECSYS_SOC */599#define CLK_VDEC1_SOC_LARB1 0600#define CLK_VDEC1_SOC_LAT 1601#define CLK_VDEC1_SOC_LAT_ACTIVE 2602#define CLK_VDEC1_SOC_LAT_ENG 3603#define CLK_VDEC1_SOC_VDEC 4604#define CLK_VDEC1_SOC_VDEC_ACTIVE 5605#define CLK_VDEC1_SOC_VDEC_ENG 6606#define CLK_VDEC1_NR_CLK 7607 608/* VDECSYS */609#define CLK_VDEC2_LARB1 0610#define CLK_VDEC2_LAT 1611#define CLK_VDEC2_VDEC 2612#define CLK_VDEC2_VDEC_ACTIVE 3613#define CLK_VDEC2_VDEC_ENG 4614#define CLK_VDEC2_NR_CLK 5615 616/* VENCSYS */617#define CLK_VENC1_LARB 0618#define CLK_VENC1_VENC 1619#define CLK_VENC1_JPGENC 2620#define CLK_VENC1_JPGDEC 3621#define CLK_VENC1_JPGDEC_C1 4622#define CLK_VENC1_GALS 5623#define CLK_VENC1_GALS_SRAM 6624#define CLK_VENC1_NR_CLK 7625 626/* VDOSYS0 */627#define CLK_VDO0_DISP_OVL0 0628#define CLK_VDO0_FAKE_ENG0 1629#define CLK_VDO0_DISP_CCORR0 2630#define CLK_VDO0_DISP_MUTEX0 3631#define CLK_VDO0_DISP_GAMMA0 4632#define CLK_VDO0_DISP_DITHER0 5633#define CLK_VDO0_DISP_WDMA0 6634#define CLK_VDO0_DISP_RDMA0 7635#define CLK_VDO0_DSI0 8636#define CLK_VDO0_DSI1 9637#define CLK_VDO0_DSC_WRAP0 10638#define CLK_VDO0_VPP_MERGE0 11639#define CLK_VDO0_DP_INTF0 12640#define CLK_VDO0_DISP_AAL0 13641#define CLK_VDO0_INLINEROT0 14642#define CLK_VDO0_APB_BUS 15643#define CLK_VDO0_DISP_COLOR0 16644#define CLK_VDO0_MDP_WROT0 17645#define CLK_VDO0_DISP_RSZ0 18646#define CLK_VDO0_DISP_POSTMASK0 19647#define CLK_VDO0_FAKE_ENG1 20648#define CLK_VDO0_DL_ASYNC2 21649#define CLK_VDO0_DL_RELAY3 22650#define CLK_VDO0_DL_RELAY4 23651#define CLK_VDO0_SMI_GALS 24652#define CLK_VDO0_SMI_COMMON 25653#define CLK_VDO0_SMI_EMI 26654#define CLK_VDO0_SMI_IOMMU 27655#define CLK_VDO0_SMI_LARB 28656#define CLK_VDO0_SMI_RSI 29657#define CLK_VDO0_DSI0_DSI 30658#define CLK_VDO0_DSI1_DSI 31659#define CLK_VDO0_DP_INTF0_DP_INTF 32660#define CLK_VDO0_NR_CLK 33661 662/* VDOSYS1 */663#define CLK_VDO1_SMI_LARB2 0664#define CLK_VDO1_SMI_LARB3 1665#define CLK_VDO1_GALS 2666#define CLK_VDO1_FAKE_ENG0 3667#define CLK_VDO1_FAKE_ENG1 4668#define CLK_VDO1_MDP_RDMA0 5669#define CLK_VDO1_MDP_RDMA1 6670#define CLK_VDO1_MDP_RDMA2 7671#define CLK_VDO1_MDP_RDMA3 8672#define CLK_VDO1_VPP_MERGE0 9673#define CLK_VDO1_VPP_MERGE1 10674#define CLK_VDO1_VPP_MERGE2 11675#define CLK_VDO1_VPP_MERGE3 12676#define CLK_VDO1_VPP_MERGE4 13677#define CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC 14678#define CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC 15679#define CLK_VDO1_DISP_MUTEX 16680#define CLK_VDO1_MDP_RDMA4 17681#define CLK_VDO1_MDP_RDMA5 18682#define CLK_VDO1_MDP_RDMA6 19683#define CLK_VDO1_MDP_RDMA7 20684#define CLK_VDO1_DP_INTF0_MMCK 21685#define CLK_VDO1_DPI0_MM 22686#define CLK_VDO1_DPI1_MM 23687#define CLK_VDO1_MERGE0_DL_ASYNC 24688#define CLK_VDO1_MERGE1_DL_ASYNC 25689#define CLK_VDO1_MERGE2_DL_ASYNC 26690#define CLK_VDO1_MERGE3_DL_ASYNC 27691#define CLK_VDO1_MERGE4_DL_ASYNC 28692#define CLK_VDO1_DSC_VDO1_DL_ASYNC 29693#define CLK_VDO1_MERGE_VDO1_DL_ASYNC 30694#define CLK_VDO1_PADDING0 31695#define CLK_VDO1_PADDING1 32696#define CLK_VDO1_PADDING2 33697#define CLK_VDO1_PADDING3 34698#define CLK_VDO1_PADDING4 35699#define CLK_VDO1_PADDING5 36700#define CLK_VDO1_PADDING6 37701#define CLK_VDO1_PADDING7 38702#define CLK_VDO1_DISP_RSZ0 39703#define CLK_VDO1_DISP_RSZ1 40704#define CLK_VDO1_DISP_RSZ2 41705#define CLK_VDO1_DISP_RSZ3 42706#define CLK_VDO1_HDR_VDO_FE0 43707#define CLK_VDO1_HDR_GFX_FE0 44708#define CLK_VDO1_HDR_VDO_BE 45709#define CLK_VDO1_HDR_VDO_FE1 46710#define CLK_VDO1_HDR_GFX_FE1 47711#define CLK_VDO1_DISP_MIXER 48712#define CLK_VDO1_HDR_VDO_FE0_DL_ASYNC 49713#define CLK_VDO1_HDR_VDO_FE1_DL_ASYNC 50714#define CLK_VDO1_HDR_GFX_FE0_DL_ASYNC 51715#define CLK_VDO1_HDR_GFX_FE1_DL_ASYNC 52716#define CLK_VDO1_HDR_VDO_BE_DL_ASYNC 53717#define CLK_VDO1_DPI0 54718#define CLK_VDO1_DISP_MONITOR_DPI0 55719#define CLK_VDO1_DPI1 56720#define CLK_VDO1_DISP_MONITOR_DPI1 57721#define CLK_VDO1_DPINTF 58722#define CLK_VDO1_DISP_MONITOR_DPINTF 59723#define CLK_VDO1_26M_SLOW 60724#define CLK_VDO1_NR_CLK 61725 726#endif /* _DT_BINDINGS_CLK_MT8188_H */727