374 lines · c
1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2 *3 * Copyright (c) 2022 MediaTek Inc.4 */5 6#ifndef _DT_BINDINGS_CLK_MT8365_H7#define _DT_BINDINGS_CLK_MT8365_H8 9/* TOPCKGEN */10#define CLK_TOP_CLK_NULL 011#define CLK_TOP_I2S0_BCK 112#define CLK_TOP_DSI0_LNTC_DSICK 213#define CLK_TOP_VPLL_DPIX 314#define CLK_TOP_LVDSTX_CLKDIG_CTS 415#define CLK_TOP_MFGPLL 516#define CLK_TOP_SYSPLL_D2 617#define CLK_TOP_SYSPLL1_D2 718#define CLK_TOP_SYSPLL1_D4 819#define CLK_TOP_SYSPLL1_D8 920#define CLK_TOP_SYSPLL1_D16 1021#define CLK_TOP_SYSPLL_D3 1122#define CLK_TOP_SYSPLL2_D2 1223#define CLK_TOP_SYSPLL2_D4 1324#define CLK_TOP_SYSPLL2_D8 1425#define CLK_TOP_SYSPLL_D5 1526#define CLK_TOP_SYSPLL3_D2 1627#define CLK_TOP_SYSPLL3_D4 1728#define CLK_TOP_SYSPLL_D7 1829#define CLK_TOP_SYSPLL4_D2 1930#define CLK_TOP_SYSPLL4_D4 2031#define CLK_TOP_UNIVPLL 2132#define CLK_TOP_UNIVPLL_D2 2233#define CLK_TOP_UNIVPLL1_D2 2334#define CLK_TOP_UNIVPLL1_D4 2435#define CLK_TOP_UNIVPLL_D3 2536#define CLK_TOP_UNIVPLL2_D2 2637#define CLK_TOP_UNIVPLL2_D4 2738#define CLK_TOP_UNIVPLL2_D8 2839#define CLK_TOP_UNIVPLL2_D32 2940#define CLK_TOP_UNIVPLL_D5 3041#define CLK_TOP_UNIVPLL3_D2 3142#define CLK_TOP_UNIVPLL3_D4 3243#define CLK_TOP_MMPLL 3344#define CLK_TOP_MMPLL_D2 3445#define CLK_TOP_LVDSPLL_D2 3546#define CLK_TOP_LVDSPLL_D4 3647#define CLK_TOP_LVDSPLL_D8 3748#define CLK_TOP_LVDSPLL_D16 3849#define CLK_TOP_USB20_192M 3950#define CLK_TOP_USB20_192M_D4 4051#define CLK_TOP_USB20_192M_D8 4152#define CLK_TOP_USB20_192M_D16 4253#define CLK_TOP_USB20_192M_D32 4354#define CLK_TOP_APLL1 4455#define CLK_TOP_APLL1_D2 4556#define CLK_TOP_APLL1_D4 4657#define CLK_TOP_APLL1_D8 4758#define CLK_TOP_APLL2 4859#define CLK_TOP_APLL2_D2 4960#define CLK_TOP_APLL2_D4 5061#define CLK_TOP_APLL2_D8 5162#define CLK_TOP_SYS_26M_D2 5263#define CLK_TOP_MSDCPLL 5364#define CLK_TOP_MSDCPLL_D2 5465#define CLK_TOP_DSPPLL 5566#define CLK_TOP_DSPPLL_D2 5667#define CLK_TOP_DSPPLL_D4 5768#define CLK_TOP_DSPPLL_D8 5869#define CLK_TOP_APUPLL 5970#define CLK_TOP_CLK26M_D52 6071#define CLK_TOP_AXI_SEL 6172#define CLK_TOP_MEM_SEL 6273#define CLK_TOP_MM_SEL 6374#define CLK_TOP_SCP_SEL 6475#define CLK_TOP_MFG_SEL 6576#define CLK_TOP_ATB_SEL 6677#define CLK_TOP_CAMTG_SEL 6778#define CLK_TOP_CAMTG1_SEL 6879#define CLK_TOP_UART_SEL 6980#define CLK_TOP_SPI_SEL 7081#define CLK_TOP_MSDC50_0_HC_SEL 7182#define CLK_TOP_MSDC2_2_HC_SEL 7283#define CLK_TOP_MSDC50_0_SEL 7384#define CLK_TOP_MSDC50_2_SEL 7485#define CLK_TOP_MSDC30_1_SEL 7586#define CLK_TOP_AUDIO_SEL 7687#define CLK_TOP_AUD_INTBUS_SEL 7788#define CLK_TOP_AUD_1_SEL 7889#define CLK_TOP_AUD_2_SEL 7990#define CLK_TOP_AUD_ENGEN1_SEL 8091#define CLK_TOP_AUD_ENGEN2_SEL 8192#define CLK_TOP_AUD_SPDIF_SEL 8293#define CLK_TOP_DISP_PWM_SEL 8394#define CLK_TOP_DXCC_SEL 8495#define CLK_TOP_SSUSB_SYS_SEL 8596#define CLK_TOP_SSUSB_XHCI_SEL 8697#define CLK_TOP_SPM_SEL 8798#define CLK_TOP_I2C_SEL 8899#define CLK_TOP_PWM_SEL 89100#define CLK_TOP_SENIF_SEL 90101#define CLK_TOP_AES_FDE_SEL 91102#define CLK_TOP_CAMTM_SEL 92103#define CLK_TOP_DPI0_SEL 93104#define CLK_TOP_DPI1_SEL 94105#define CLK_TOP_DSP_SEL 95106#define CLK_TOP_NFI2X_SEL 96107#define CLK_TOP_NFIECC_SEL 97108#define CLK_TOP_ECC_SEL 98109#define CLK_TOP_ETH_SEL 99110#define CLK_TOP_GCPU_SEL 100111#define CLK_TOP_GCPU_CPM_SEL 101112#define CLK_TOP_APU_SEL 102113#define CLK_TOP_APU_IF_SEL 103114#define CLK_TOP_MBIST_DIAG_SEL 104115#define CLK_TOP_APLL_I2S0_SEL 105116#define CLK_TOP_APLL_I2S1_SEL 106117#define CLK_TOP_APLL_I2S2_SEL 107118#define CLK_TOP_APLL_I2S3_SEL 108119#define CLK_TOP_APLL_TDMOUT_SEL 109120#define CLK_TOP_APLL_TDMIN_SEL 110121#define CLK_TOP_APLL_SPDIF_SEL 111122#define CLK_TOP_APLL12_CK_DIV0 112123#define CLK_TOP_APLL12_CK_DIV1 113124#define CLK_TOP_APLL12_CK_DIV2 114125#define CLK_TOP_APLL12_CK_DIV3 115126#define CLK_TOP_APLL12_CK_DIV4 116127#define CLK_TOP_APLL12_CK_DIV4B 117128#define CLK_TOP_APLL12_CK_DIV5 118129#define CLK_TOP_APLL12_CK_DIV5B 119130#define CLK_TOP_APLL12_CK_DIV6 120131#define CLK_TOP_AUD_I2S0_M 121132#define CLK_TOP_AUD_I2S1_M 122133#define CLK_TOP_AUD_I2S2_M 123134#define CLK_TOP_AUD_I2S3_M 124135#define CLK_TOP_AUD_TDMOUT_M 125136#define CLK_TOP_AUD_TDMOUT_B 126137#define CLK_TOP_AUD_TDMIN_M 127138#define CLK_TOP_AUD_TDMIN_B 128139#define CLK_TOP_AUD_SPDIF_M 129140#define CLK_TOP_USB20_48M_EN 130141#define CLK_TOP_UNIVPLL_48M_EN 131142#define CLK_TOP_LVDSTX_CLKDIG_EN 132143#define CLK_TOP_VPLL_DPIX_EN 133144#define CLK_TOP_SSUSB_TOP_CK_EN 134145#define CLK_TOP_SSUSB_PHY_CK_EN 135146#define CLK_TOP_CONN_32K 136147#define CLK_TOP_CONN_26M 137148#define CLK_TOP_DSP_32K 138149#define CLK_TOP_DSP_26M 139150#define CLK_TOP_NR_CLK 140151 152/* INFRACFG */153#define CLK_IFR_PMIC_TMR 0154#define CLK_IFR_PMIC_AP 1155#define CLK_IFR_PMIC_MD 2156#define CLK_IFR_PMIC_CONN 3157#define CLK_IFR_ICUSB 4158#define CLK_IFR_GCE 5159#define CLK_IFR_THERM 6160#define CLK_IFR_PWM_HCLK 7161#define CLK_IFR_PWM1 8162#define CLK_IFR_PWM2 9163#define CLK_IFR_PWM3 10164#define CLK_IFR_PWM4 11165#define CLK_IFR_PWM5 12166#define CLK_IFR_PWM 13167#define CLK_IFR_UART0 14168#define CLK_IFR_UART1 15169#define CLK_IFR_UART2 16170#define CLK_IFR_DSP_UART 17171#define CLK_IFR_GCE_26M 18172#define CLK_IFR_CQ_DMA_FPC 19173#define CLK_IFR_BTIF 20174#define CLK_IFR_SPI0 21175#define CLK_IFR_MSDC0_HCLK 22176#define CLK_IFR_MSDC2_HCLK 23177#define CLK_IFR_MSDC1_HCLK 24178#define CLK_IFR_DVFSRC 25179#define CLK_IFR_GCPU 26180#define CLK_IFR_TRNG 27181#define CLK_IFR_AUXADC 28182#define CLK_IFR_CPUM 29183#define CLK_IFR_AUXADC_MD 30184#define CLK_IFR_AP_DMA 31185#define CLK_IFR_DEBUGSYS 32186#define CLK_IFR_AUDIO 33187#define CLK_IFR_PWM_FBCLK6 34188#define CLK_IFR_DISP_PWM 35189#define CLK_IFR_AUD_26M_BK 36190#define CLK_IFR_CQ_DMA 37191#define CLK_IFR_MSDC0_SF 38192#define CLK_IFR_MSDC1_SF 39193#define CLK_IFR_MSDC2_SF 40194#define CLK_IFR_AP_MSDC0 41195#define CLK_IFR_MD_MSDC0 42196#define CLK_IFR_MSDC0_SRC 43197#define CLK_IFR_MSDC1_SRC 44198#define CLK_IFR_MSDC2_SRC 45199#define CLK_IFR_PWRAP_TMR 46200#define CLK_IFR_PWRAP_SPI 47201#define CLK_IFR_PWRAP_SYS 48202#define CLK_IFR_MCU_PM_BK 49203#define CLK_IFR_IRRX_26M 50204#define CLK_IFR_IRRX_32K 51205#define CLK_IFR_I2C0_AXI 52206#define CLK_IFR_I2C1_AXI 53207#define CLK_IFR_I2C2_AXI 54208#define CLK_IFR_I2C3_AXI 55209#define CLK_IFR_NIC_AXI 56210#define CLK_IFR_NIC_SLV_AXI 57211#define CLK_IFR_APU_AXI 58212#define CLK_IFR_NFIECC 59213#define CLK_IFR_NFIECC_BK 60214#define CLK_IFR_NFI1X_BK 61215#define CLK_IFR_NFI_BK 62216#define CLK_IFR_MSDC2_AP_BK 63217#define CLK_IFR_MSDC2_MD_BK 64218#define CLK_IFR_MSDC2_BK 65219#define CLK_IFR_SUSB_133_BK 66220#define CLK_IFR_SUSB_66_BK 67221#define CLK_IFR_SSUSB_SYS 68222#define CLK_IFR_SSUSB_REF 69223#define CLK_IFR_SSUSB_XHCI 70224#define CLK_IFR_NR_CLK 71225 226/* PERICFG */227#define CLK_PERIAXI 0228#define CLK_PERI_NR_CLK 1229 230/* APMIXEDSYS */231#define CLK_APMIXED_ARMPLL 0232#define CLK_APMIXED_MAINPLL 1233#define CLK_APMIXED_UNIVPLL 2234#define CLK_APMIXED_MFGPLL 3235#define CLK_APMIXED_MSDCPLL 4236#define CLK_APMIXED_MMPLL 5237#define CLK_APMIXED_APLL1 6238#define CLK_APMIXED_APLL2 7239#define CLK_APMIXED_LVDSPLL 8240#define CLK_APMIXED_DSPPLL 9241#define CLK_APMIXED_APUPLL 10242#define CLK_APMIXED_UNIV_EN 11243#define CLK_APMIXED_USB20_EN 12244#define CLK_APMIXED_NR_CLK 13245 246/* GCE */247#define CLK_GCE_FAXI 0248#define CLK_GCE_NR_CLK 1249 250/* AUDIOTOP */251#define CLK_AUD_AFE 0252#define CLK_AUD_I2S 1253#define CLK_AUD_22M 2254#define CLK_AUD_24M 3255#define CLK_AUD_INTDIR 4256#define CLK_AUD_APLL2_TUNER 5257#define CLK_AUD_APLL_TUNER 6258#define CLK_AUD_SPDF 7259#define CLK_AUD_HDMI 8260#define CLK_AUD_HDMI_IN 9261#define CLK_AUD_ADC 10262#define CLK_AUD_DAC 11263#define CLK_AUD_DAC_PREDIS 12264#define CLK_AUD_TML 13265#define CLK_AUD_I2S1_BK 14266#define CLK_AUD_I2S2_BK 15267#define CLK_AUD_I2S3_BK 16268#define CLK_AUD_I2S4_BK 17269#define CLK_AUD_NR_CLK 18270 271/* MIPI_CSI0A */272#define CLK_MIPI0A_CSR_CSI_EN_0A 0273#define CLK_MIPI_RX_ANA_CSI0A_NR_CLK 1274 275/* MIPI_CSI0B */276#define CLK_MIPI0B_CSR_CSI_EN_0B 0277#define CLK_MIPI_RX_ANA_CSI0B_NR_CLK 1278 279/* MIPI_CSI1A */280#define CLK_MIPI1A_CSR_CSI_EN_1A 0281#define CLK_MIPI_RX_ANA_CSI1A_NR_CLK 1282 283/* MIPI_CSI1B */284#define CLK_MIPI1B_CSR_CSI_EN_1B 0285#define CLK_MIPI_RX_ANA_CSI1B_NR_CLK 1286 287/* MIPI_CSI2A */288#define CLK_MIPI2A_CSR_CSI_EN_2A 0289#define CLK_MIPI_RX_ANA_CSI2A_NR_CLK 1290 291/* MIPI_CSI2B */292#define CLK_MIPI2B_CSR_CSI_EN_2B 0293#define CLK_MIPI_RX_ANA_CSI2B_NR_CLK 1294 295/* MCUCFG */296#define CLK_MCU_BUS_SEL 0297#define CLK_MCU_NR_CLK 1298 299/* MFGCFG */300#define CLK_MFG_BG3D 0301#define CLK_MFG_MBIST_DIAG 1302#define CLK_MFG_NR_CLK 2303 304/* MMSYS */305#define CLK_MM_MM_MDP_RDMA0 0306#define CLK_MM_MM_MDP_CCORR0 1307#define CLK_MM_MM_MDP_RSZ0 2308#define CLK_MM_MM_MDP_RSZ1 3309#define CLK_MM_MM_MDP_TDSHP0 4310#define CLK_MM_MM_MDP_WROT0 5311#define CLK_MM_MM_MDP_WDMA0 6312#define CLK_MM_MM_DISP_OVL0 7313#define CLK_MM_MM_DISP_OVL0_2L 8314#define CLK_MM_MM_DISP_RSZ0 9315#define CLK_MM_MM_DISP_RDMA0 10316#define CLK_MM_MM_DISP_WDMA0 11317#define CLK_MM_MM_DISP_COLOR0 12318#define CLK_MM_MM_DISP_CCORR0 13319#define CLK_MM_MM_DISP_AAL0 14320#define CLK_MM_MM_DISP_GAMMA0 15321#define CLK_MM_MM_DISP_DITHER0 16322#define CLK_MM_MM_DSI0 17323#define CLK_MM_MM_DISP_RDMA1 18324#define CLK_MM_MM_MDP_RDMA1 19325#define CLK_MM_DPI0_DPI0 20326#define CLK_MM_MM_FAKE 21327#define CLK_MM_MM_SMI_COMMON 22328#define CLK_MM_MM_SMI_LARB0 23329#define CLK_MM_MM_SMI_COMM0 24330#define CLK_MM_MM_SMI_COMM1 25331#define CLK_MM_MM_CAM_MDP 26332#define CLK_MM_MM_SMI_IMG 27333#define CLK_MM_MM_SMI_CAM 28334#define CLK_MM_IMG_IMG_DL_RELAY 29335#define CLK_MM_IMG_IMG_DL_ASYNC_TOP 30336#define CLK_MM_DSI0_DIG_DSI 31337#define CLK_MM_26M_HRTWT 32338#define CLK_MM_MM_DPI0 33339#define CLK_MM_LVDSTX_PXL 34340#define CLK_MM_LVDSTX_CTS 35341#define CLK_MM_NR_CLK 36342 343/* IMGSYS */344#define CLK_CAM_LARB2 0345#define CLK_CAM 1346#define CLK_CAMTG 2347#define CLK_CAM_SENIF 3348#define CLK_CAMSV0 4349#define CLK_CAMSV1 5350#define CLK_CAM_FDVT 6351#define CLK_CAM_WPE 7352#define CLK_CAM_NR_CLK 8353 354/* VDECSYS */355#define CLK_VDEC_VDEC 0356#define CLK_VDEC_LARB1 1357#define CLK_VDEC_NR_CLK 2358 359/* VENCSYS */360#define CLK_VENC 0361#define CLK_VENC_JPGENC 1362#define CLK_VENC_NR_CLK 2363 364/* APUSYS */365#define CLK_APU_IPU_CK 0366#define CLK_APU_AXI 1367#define CLK_APU_JTAG 2368#define CLK_APU_IF_CK 3369#define CLK_APU_EDMA 4370#define CLK_APU_AHB 5371#define CLK_APU_NR_CLK 6372 373#endif /* _DT_BINDINGS_CLK_MT8365_H */374