77 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Daire McNamara,<daire.mcnamara@microchip.com>4 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.5 */6 7#ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_8#define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_9 10#define CLK_CPU 011#define CLK_AXI 112#define CLK_AHB 213 14#define CLK_ENVM 315#define CLK_MAC0 416#define CLK_MAC1 517#define CLK_MMC 618#define CLK_TIMER 719#define CLK_MMUART0 820#define CLK_MMUART1 921#define CLK_MMUART2 1022#define CLK_MMUART3 1123#define CLK_MMUART4 1224#define CLK_SPI0 1325#define CLK_SPI1 1426#define CLK_I2C0 1527#define CLK_I2C1 1628#define CLK_CAN0 1729#define CLK_CAN1 1830#define CLK_USB 1931#define CLK_RESERVED 2032#define CLK_RTC 2133#define CLK_QSPI 2234#define CLK_GPIO0 2335#define CLK_GPIO1 2436#define CLK_GPIO2 2537#define CLK_DDRC 2638#define CLK_FIC0 2739#define CLK_FIC1 2840#define CLK_FIC2 2941#define CLK_FIC3 3042#define CLK_ATHENA 3143#define CLK_CFM 3244 45#define CLK_RTCREF 3346#define CLK_MSSPLL 3447#define CLK_MSSPLL0 3448#define CLK_MSSPLL1 3549#define CLK_MSSPLL2 3650#define CLK_MSSPLL3 3751/* 38 is reserved for MSS PLL internals */52 53/* Clock Conditioning Circuitry Clock IDs */54 55#define CLK_CCC_PLL0 056#define CLK_CCC_PLL1 157#define CLK_CCC_DLL0 258#define CLK_CCC_DLL1 359 60#define CLK_CCC_PLL0_OUT0 461#define CLK_CCC_PLL0_OUT1 562#define CLK_CCC_PLL0_OUT2 663#define CLK_CCC_PLL0_OUT3 764 65#define CLK_CCC_PLL1_OUT0 866#define CLK_CCC_PLL1_OUT1 967#define CLK_CCC_PLL1_OUT2 1068#define CLK_CCC_PLL1_OUT3 1169 70#define CLK_CCC_DLL0_OUT0 1271#define CLK_CCC_DLL0_OUT1 1372 73#define CLK_CCC_DLL1_OUT0 1474#define CLK_CCC_DLL1_OUT1 1575 76#endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */77