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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2014 MediaTek Inc.4 * Author: Shunli Wang <shunli.wang@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_CLK_MT2701_H8#define _DT_BINDINGS_CLK_MT2701_H9 10/* TOPCKGEN */11#define CLK_TOP_SYSPLL 112#define CLK_TOP_SYSPLL_D2 213#define CLK_TOP_SYSPLL_D3 314#define CLK_TOP_SYSPLL_D5 415#define CLK_TOP_SYSPLL_D7 516#define CLK_TOP_SYSPLL1_D2 617#define CLK_TOP_SYSPLL1_D4 718#define CLK_TOP_SYSPLL1_D8 819#define CLK_TOP_SYSPLL1_D16 920#define CLK_TOP_SYSPLL2_D2 1021#define CLK_TOP_SYSPLL2_D4 1122#define CLK_TOP_SYSPLL2_D8 1223#define CLK_TOP_SYSPLL3_D2 1324#define CLK_TOP_SYSPLL3_D4 1425#define CLK_TOP_SYSPLL4_D2 1526#define CLK_TOP_SYSPLL4_D4 1627#define CLK_TOP_UNIVPLL 1728#define CLK_TOP_UNIVPLL_D2 1829#define CLK_TOP_UNIVPLL_D3 1930#define CLK_TOP_UNIVPLL_D5 2031#define CLK_TOP_UNIVPLL_D7 2132#define CLK_TOP_UNIVPLL_D26 2233#define CLK_TOP_UNIVPLL_D52 2334#define CLK_TOP_UNIVPLL_D108 2435#define CLK_TOP_USB_PHY48M 2536#define CLK_TOP_UNIVPLL1_D2 2637#define CLK_TOP_UNIVPLL1_D4 2738#define CLK_TOP_UNIVPLL1_D8 2839#define CLK_TOP_UNIVPLL2_D2 2940#define CLK_TOP_UNIVPLL2_D4 3041#define CLK_TOP_UNIVPLL2_D8 3142#define CLK_TOP_UNIVPLL2_D16 3243#define CLK_TOP_UNIVPLL2_D32 3344#define CLK_TOP_UNIVPLL3_D2 3445#define CLK_TOP_UNIVPLL3_D4 3546#define CLK_TOP_UNIVPLL3_D8 3647#define CLK_TOP_MSDCPLL 3748#define CLK_TOP_MSDCPLL_D2 3849#define CLK_TOP_MSDCPLL_D4 3950#define CLK_TOP_MSDCPLL_D8 4051#define CLK_TOP_MMPLL 4152#define CLK_TOP_MMPLL_D2 4253#define CLK_TOP_DMPLL 4354#define CLK_TOP_DMPLL_D2 4455#define CLK_TOP_DMPLL_D4 4556#define CLK_TOP_DMPLL_X2 4657#define CLK_TOP_TVDPLL 4758#define CLK_TOP_TVDPLL_D2 4859#define CLK_TOP_TVDPLL_D4 4960#define CLK_TOP_TVD2PLL 5061#define CLK_TOP_TVD2PLL_D2 5162#define CLK_TOP_HADDS2PLL_98M 5263#define CLK_TOP_HADDS2PLL_294M 5364#define CLK_TOP_HADDS2_FB 5465#define CLK_TOP_MIPIPLL_D2 5566#define CLK_TOP_MIPIPLL_D4 5667#define CLK_TOP_HDMIPLL 5768#define CLK_TOP_HDMIPLL_D2 5869#define CLK_TOP_HDMIPLL_D3 5970#define CLK_TOP_HDMI_SCL_RX 6071#define CLK_TOP_HDMI_0_PIX340M 6172#define CLK_TOP_HDMI_0_DEEP340M 6273#define CLK_TOP_HDMI_0_PLL340M 6374#define CLK_TOP_AUD1PLL_98M 6475#define CLK_TOP_AUD2PLL_90M 6576#define CLK_TOP_AUDPLL 6677#define CLK_TOP_AUDPLL_D4 6778#define CLK_TOP_AUDPLL_D8 6879#define CLK_TOP_AUDPLL_D16 6980#define CLK_TOP_AUDPLL_D24 7081#define CLK_TOP_ETHPLL_500M 7182#define CLK_TOP_VDECPLL 7283#define CLK_TOP_VENCPLL 7384#define CLK_TOP_MIPIPLL 7485#define CLK_TOP_ARMPLL_1P3G 7586 87#define CLK_TOP_MM_SEL 7688#define CLK_TOP_DDRPHYCFG_SEL 7789#define CLK_TOP_MEM_SEL 7890#define CLK_TOP_AXI_SEL 7991#define CLK_TOP_CAMTG_SEL 8092#define CLK_TOP_MFG_SEL 8193#define CLK_TOP_VDEC_SEL 8294#define CLK_TOP_PWM_SEL 8395#define CLK_TOP_MSDC30_0_SEL 8496#define CLK_TOP_USB20_SEL 8597#define CLK_TOP_SPI0_SEL 8698#define CLK_TOP_UART_SEL 8799#define CLK_TOP_AUDINTBUS_SEL 88100#define CLK_TOP_AUDIO_SEL 89101#define CLK_TOP_MSDC30_2_SEL 90102#define CLK_TOP_MSDC30_1_SEL 91103#define CLK_TOP_DPI1_SEL 92104#define CLK_TOP_DPI0_SEL 93105#define CLK_TOP_SCP_SEL 94106#define CLK_TOP_PMICSPI_SEL 95107#define CLK_TOP_APLL_SEL 96108#define CLK_TOP_HDMI_SEL 97109#define CLK_TOP_TVE_SEL 98110#define CLK_TOP_EMMC_HCLK_SEL 99111#define CLK_TOP_NFI2X_SEL 100112#define CLK_TOP_RTC_SEL 101113#define CLK_TOP_OSD_SEL 102114#define CLK_TOP_NR_SEL 103115#define CLK_TOP_DI_SEL 104116#define CLK_TOP_FLASH_SEL 105117#define CLK_TOP_ASM_M_SEL 106118#define CLK_TOP_ASM_I_SEL 107119#define CLK_TOP_INTDIR_SEL 108120#define CLK_TOP_HDMIRX_BIST_SEL 109121#define CLK_TOP_ETHIF_SEL 110122#define CLK_TOP_MS_CARD_SEL 111123#define CLK_TOP_ASM_H_SEL 112124#define CLK_TOP_SPI1_SEL 113125#define CLK_TOP_CMSYS_SEL 114126#define CLK_TOP_MSDC30_3_SEL 115127#define CLK_TOP_HDMIRX26_24_SEL 116128#define CLK_TOP_AUD2DVD_SEL 117129#define CLK_TOP_8BDAC_SEL 118130#define CLK_TOP_SPI2_SEL 119131#define CLK_TOP_AUD_MUX1_SEL 120132#define CLK_TOP_AUD_MUX2_SEL 121133#define CLK_TOP_AUDPLL_MUX_SEL 122134#define CLK_TOP_AUD_K1_SRC_SEL 123135#define CLK_TOP_AUD_K2_SRC_SEL 124136#define CLK_TOP_AUD_K3_SRC_SEL 125137#define CLK_TOP_AUD_K4_SRC_SEL 126138#define CLK_TOP_AUD_K5_SRC_SEL 127139#define CLK_TOP_AUD_K6_SRC_SEL 128140#define CLK_TOP_PADMCLK_SEL 129141#define CLK_TOP_AUD_EXTCK1_DIV 130142#define CLK_TOP_AUD_EXTCK2_DIV 131143#define CLK_TOP_AUD_MUX1_DIV 132144#define CLK_TOP_AUD_MUX2_DIV 133145#define CLK_TOP_AUD_K1_SRC_DIV 134146#define CLK_TOP_AUD_K2_SRC_DIV 135147#define CLK_TOP_AUD_K3_SRC_DIV 136148#define CLK_TOP_AUD_K4_SRC_DIV 137149#define CLK_TOP_AUD_K5_SRC_DIV 138150#define CLK_TOP_AUD_K6_SRC_DIV 139151#define CLK_TOP_AUD_I2S1_MCLK 140152#define CLK_TOP_AUD_I2S2_MCLK 141153#define CLK_TOP_AUD_I2S3_MCLK 142154#define CLK_TOP_AUD_I2S4_MCLK 143155#define CLK_TOP_AUD_I2S5_MCLK 144156#define CLK_TOP_AUD_I2S6_MCLK 145157#define CLK_TOP_AUD_48K_TIMING 146158#define CLK_TOP_AUD_44K_TIMING 147159 160#define CLK_TOP_32K_INTERNAL 148161#define CLK_TOP_32K_EXTERNAL 149162#define CLK_TOP_CLK26M_D8 150163#define CLK_TOP_8BDAC 151164#define CLK_TOP_WBG_DIG_416M 152165#define CLK_TOP_DPI 153166#define CLK_TOP_DSI0_LNTC_DSI 154167#define CLK_TOP_AUD_EXT1 155168#define CLK_TOP_AUD_EXT2 156169#define CLK_TOP_NFI1X_PAD 157170#define CLK_TOP_AXISEL_D4 158171#define CLK_TOP_NR 159172 173/* APMIXEDSYS */174 175#define CLK_APMIXED_ARMPLL 1176#define CLK_APMIXED_MAINPLL 2177#define CLK_APMIXED_UNIVPLL 3178#define CLK_APMIXED_MMPLL 4179#define CLK_APMIXED_MSDCPLL 5180#define CLK_APMIXED_TVDPLL 6181#define CLK_APMIXED_AUD1PLL 7182#define CLK_APMIXED_TRGPLL 8183#define CLK_APMIXED_ETHPLL 9184#define CLK_APMIXED_VDECPLL 10185#define CLK_APMIXED_HADDS2PLL 11186#define CLK_APMIXED_AUD2PLL 12187#define CLK_APMIXED_TVD2PLL 13188#define CLK_APMIXED_HDMI_REF 14189#define CLK_APMIXED_NR 15190 191/* DDRPHY */192 193#define CLK_DDRPHY_VENCPLL 1194#define CLK_DDRPHY_NR 2195 196/* INFRACFG */197 198#define CLK_INFRA_DBG 1199#define CLK_INFRA_SMI 2200#define CLK_INFRA_QAXI_CM4 3201#define CLK_INFRA_AUD_SPLIN_B 4202#define CLK_INFRA_AUDIO 5203#define CLK_INFRA_EFUSE 6204#define CLK_INFRA_L2C_SRAM 7205#define CLK_INFRA_M4U 8206#define CLK_INFRA_CONNMCU 9207#define CLK_INFRA_TRNG 10208#define CLK_INFRA_RAMBUFIF 11209#define CLK_INFRA_CPUM 12210#define CLK_INFRA_KP 13211#define CLK_INFRA_CEC 14212#define CLK_INFRA_IRRX 15213#define CLK_INFRA_PMICSPI 16214#define CLK_INFRA_PMICWRAP 17215#define CLK_INFRA_DDCCI 18216#define CLK_INFRA_CLK_13M 19217#define CLK_INFRA_CPUSEL 20218#define CLK_INFRA_NR 21219 220/* PERICFG */221 222#define CLK_PERI_NFI 1223#define CLK_PERI_THERM 2224#define CLK_PERI_PWM1 3225#define CLK_PERI_PWM2 4226#define CLK_PERI_PWM3 5227#define CLK_PERI_PWM4 6228#define CLK_PERI_PWM5 7229#define CLK_PERI_PWM6 8230#define CLK_PERI_PWM7 9231#define CLK_PERI_PWM 10232#define CLK_PERI_USB0 11233#define CLK_PERI_USB1 12234#define CLK_PERI_AP_DMA 13235#define CLK_PERI_MSDC30_0 14236#define CLK_PERI_MSDC30_1 15237#define CLK_PERI_MSDC30_2 16238#define CLK_PERI_MSDC30_3 17239#define CLK_PERI_MSDC50_3 18240#define CLK_PERI_NLI 19241#define CLK_PERI_UART0 20242#define CLK_PERI_UART1 21243#define CLK_PERI_UART2 22244#define CLK_PERI_UART3 23245#define CLK_PERI_BTIF 24246#define CLK_PERI_I2C0 25247#define CLK_PERI_I2C1 26248#define CLK_PERI_I2C2 27249#define CLK_PERI_I2C3 28250#define CLK_PERI_AUXADC 29251#define CLK_PERI_SPI0 30252#define CLK_PERI_ETH 31253#define CLK_PERI_USB0_MCU 32254 255#define CLK_PERI_USB1_MCU 33256#define CLK_PERI_USB_SLV 34257#define CLK_PERI_GCPU 35258#define CLK_PERI_NFI_ECC 36259#define CLK_PERI_NFI_PAD 37260#define CLK_PERI_FLASH 38261#define CLK_PERI_HOST89_INT 39262#define CLK_PERI_HOST89_SPI 40263#define CLK_PERI_HOST89_DVD 41264#define CLK_PERI_SPI1 42265#define CLK_PERI_SPI2 43266#define CLK_PERI_FCI 44267 268#define CLK_PERI_UART0_SEL 45269#define CLK_PERI_UART1_SEL 46270#define CLK_PERI_UART2_SEL 47271#define CLK_PERI_UART3_SEL 48272#define CLK_PERI_NR 49273 274/* AUDIO */275 276#define CLK_AUD_AFE 1277#define CLK_AUD_LRCK_DETECT 2278#define CLK_AUD_I2S 3279#define CLK_AUD_APLL_TUNER 4280#define CLK_AUD_HDMI 5281#define CLK_AUD_SPDF 6282#define CLK_AUD_SPDF2 7283#define CLK_AUD_APLL 8284#define CLK_AUD_TML 9285#define CLK_AUD_AHB_IDLE_EXT 10286#define CLK_AUD_AHB_IDLE_INT 11287 288#define CLK_AUD_I2SIN1 12289#define CLK_AUD_I2SIN2 13290#define CLK_AUD_I2SIN3 14291#define CLK_AUD_I2SIN4 15292#define CLK_AUD_I2SIN5 16293#define CLK_AUD_I2SIN6 17294#define CLK_AUD_I2SO1 18295#define CLK_AUD_I2SO2 19296#define CLK_AUD_I2SO3 20297#define CLK_AUD_I2SO4 21298#define CLK_AUD_I2SO5 22299#define CLK_AUD_I2SO6 23300#define CLK_AUD_ASRCI1 24301#define CLK_AUD_ASRCI2 25302#define CLK_AUD_ASRCO1 26303#define CLK_AUD_ASRCO2 27304#define CLK_AUD_ASRC11 28305#define CLK_AUD_ASRC12 29306#define CLK_AUD_HDMIRX 30307#define CLK_AUD_INTDIR 31308#define CLK_AUD_A1SYS 32309#define CLK_AUD_A2SYS 33310#define CLK_AUD_AFE_CONN 34311#define CLK_AUD_AFE_PCMIF 35312#define CLK_AUD_AFE_MRGIF 36313 314#define CLK_AUD_MMIF_UL1 37315#define CLK_AUD_MMIF_UL2 38316#define CLK_AUD_MMIF_UL3 39317#define CLK_AUD_MMIF_UL4 40318#define CLK_AUD_MMIF_UL5 41319#define CLK_AUD_MMIF_UL6 42320#define CLK_AUD_MMIF_DL1 43321#define CLK_AUD_MMIF_DL2 44322#define CLK_AUD_MMIF_DL3 45323#define CLK_AUD_MMIF_DL4 46324#define CLK_AUD_MMIF_DL5 47325#define CLK_AUD_MMIF_DL6 48326#define CLK_AUD_MMIF_DLMCH 49327#define CLK_AUD_MMIF_ARB1 50328#define CLK_AUD_MMIF_AWB1 51329#define CLK_AUD_MMIF_AWB2 52330#define CLK_AUD_MMIF_DAI 53331 332#define CLK_AUD_DMIC1 54333#define CLK_AUD_DMIC2 55334#define CLK_AUD_ASRCI3 56335#define CLK_AUD_ASRCI4 57336#define CLK_AUD_ASRCI5 58337#define CLK_AUD_ASRCI6 59338#define CLK_AUD_ASRCO3 60339#define CLK_AUD_ASRCO4 61340#define CLK_AUD_ASRCO5 62341#define CLK_AUD_ASRCO6 63342#define CLK_AUD_MEM_ASRC1 64343#define CLK_AUD_MEM_ASRC2 65344#define CLK_AUD_MEM_ASRC3 66345#define CLK_AUD_MEM_ASRC4 67346#define CLK_AUD_MEM_ASRC5 68347#define CLK_AUD_DSD_ENC 69348#define CLK_AUD_ASRC_BRG 70349#define CLK_AUD_NR 71350 351/* MMSYS */352 353#define CLK_MM_SMI_COMMON 1354#define CLK_MM_SMI_LARB0 2355#define CLK_MM_CMDQ 3356#define CLK_MM_MUTEX 4357#define CLK_MM_DISP_COLOR 5358#define CLK_MM_DISP_BLS 6359#define CLK_MM_DISP_WDMA 7360#define CLK_MM_DISP_RDMA 8361#define CLK_MM_DISP_OVL 9362#define CLK_MM_MDP_TDSHP 10363#define CLK_MM_MDP_WROT 11364#define CLK_MM_MDP_WDMA 12365#define CLK_MM_MDP_RSZ1 13366#define CLK_MM_MDP_RSZ0 14367#define CLK_MM_MDP_RDMA 15368#define CLK_MM_MDP_BLS_26M 16369#define CLK_MM_CAM_MDP 17370#define CLK_MM_FAKE_ENG 18371#define CLK_MM_MUTEX_32K 19372#define CLK_MM_DISP_RDMA1 20373#define CLK_MM_DISP_UFOE 21374 375#define CLK_MM_DSI_ENGINE 22376#define CLK_MM_DSI_DIG 23377#define CLK_MM_DPI_DIGL 24378#define CLK_MM_DPI_ENGINE 25379#define CLK_MM_DPI1_DIGL 26380#define CLK_MM_DPI1_ENGINE 27381#define CLK_MM_TVE_OUTPUT 28382#define CLK_MM_TVE_INPUT 29383#define CLK_MM_HDMI_PIXEL 30384#define CLK_MM_HDMI_PLL 31385#define CLK_MM_HDMI_AUDIO 32386#define CLK_MM_HDMI_SPDIF 33387#define CLK_MM_TVE_FMM 34388#define CLK_MM_NR 35389 390/* IMGSYS */391 392#define CLK_IMG_SMI_COMM 1393#define CLK_IMG_RESZ 2394#define CLK_IMG_JPGDEC_SMI 3395#define CLK_IMG_JPGDEC 4396#define CLK_IMG_VENC_LT 5397#define CLK_IMG_VENC 6398#define CLK_IMG_NR 7399 400/* VDEC */401 402#define CLK_VDEC_CKGEN 1403#define CLK_VDEC_LARB 2404#define CLK_VDEC_NR 3405 406/* HIFSYS */407 408#define CLK_HIFSYS_USB0PHY 1409#define CLK_HIFSYS_USB1PHY 2410#define CLK_HIFSYS_PCIE0 3411#define CLK_HIFSYS_PCIE1 4412#define CLK_HIFSYS_PCIE2 5413#define CLK_HIFSYS_NR 6414 415/* ETHSYS */416#define CLK_ETHSYS_HSDMA 1417#define CLK_ETHSYS_ESW 2418#define CLK_ETHSYS_GP2 3419#define CLK_ETHSYS_GP1 4420#define CLK_ETHSYS_PCM 5421#define CLK_ETHSYS_GDMA 6422#define CLK_ETHSYS_I2S 7423#define CLK_ETHSYS_CRYPTO 8424#define CLK_ETHSYS_NR 9425 426/* G3DSYS */427#define CLK_G3DSYS_CORE 1428#define CLK_G3DSYS_NR 2429 430/* BDP */431 432#define CLK_BDP_BRG_BA 1433#define CLK_BDP_BRG_DRAM 2434#define CLK_BDP_LARB_DRAM 3435#define CLK_BDP_WR_VDI_PXL 4436#define CLK_BDP_WR_VDI_DRAM 5437#define CLK_BDP_WR_B 6438#define CLK_BDP_DGI_IN 7439#define CLK_BDP_DGI_OUT 8440#define CLK_BDP_FMT_MAST_27 9441#define CLK_BDP_FMT_B 10442#define CLK_BDP_OSD_B 11443#define CLK_BDP_OSD_DRAM 12444#define CLK_BDP_OSD_AGENT 13445#define CLK_BDP_OSD_PXL 14446#define CLK_BDP_RLE_B 15447#define CLK_BDP_RLE_AGENT 16448#define CLK_BDP_RLE_DRAM 17449#define CLK_BDP_F27M 18450#define CLK_BDP_F27M_VDOUT 19451#define CLK_BDP_F27_74_74 20452#define CLK_BDP_F2FS 21453#define CLK_BDP_F2FS74_148 22454#define CLK_BDP_FB 23455#define CLK_BDP_VDO_DRAM 24456#define CLK_BDP_VDO_2FS 25457#define CLK_BDP_VDO_B 26458#define CLK_BDP_WR_DI_PXL 27459#define CLK_BDP_WR_DI_DRAM 28460#define CLK_BDP_WR_DI_B 29461#define CLK_BDP_NR_PXL 30462#define CLK_BDP_NR_DRAM 31463#define CLK_BDP_NR_B 32464 465#define CLK_BDP_RX_F 33466#define CLK_BDP_RX_X 34467#define CLK_BDP_RXPDT 35468#define CLK_BDP_RX_CSCL_N 36469#define CLK_BDP_RX_CSCL 37470#define CLK_BDP_RX_DDCSCL_N 38471#define CLK_BDP_RX_DDCSCL 39472#define CLK_BDP_RX_VCO 40473#define CLK_BDP_RX_DP 41474#define CLK_BDP_RX_P 42475#define CLK_BDP_RX_M 43476#define CLK_BDP_RX_PLL 44477#define CLK_BDP_BRG_RT_B 45478#define CLK_BDP_BRG_RT_DRAM 46479#define CLK_BDP_LARBRT_DRAM 47480#define CLK_BDP_TMDS_SYN 48481#define CLK_BDP_HDMI_MON 49482#define CLK_BDP_NR 50483 484#endif /* _DT_BINDINGS_CLK_MT2701_H */485