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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2017 MediaTek Inc.4 * Author: Weiyi Lu <weiyi.lu@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_CLK_MT2712_H8#define _DT_BINDINGS_CLK_MT2712_H9 10/* APMIXEDSYS */11 12#define CLK_APMIXED_MAINPLL 013#define CLK_APMIXED_UNIVPLL 114#define CLK_APMIXED_VCODECPLL 215#define CLK_APMIXED_VENCPLL 316#define CLK_APMIXED_APLL1 417#define CLK_APMIXED_APLL2 518#define CLK_APMIXED_LVDSPLL 619#define CLK_APMIXED_LVDSPLL2 720#define CLK_APMIXED_MSDCPLL 821#define CLK_APMIXED_MSDCPLL2 922#define CLK_APMIXED_TVDPLL 1023#define CLK_APMIXED_MMPLL 1124#define CLK_APMIXED_ARMCA35PLL 1225#define CLK_APMIXED_ARMCA72PLL 1326#define CLK_APMIXED_ETHERPLL 1427#define CLK_APMIXED_NR_CLK 1528 29/* TOPCKGEN */30 31#define CLK_TOP_ARMCA35PLL 032#define CLK_TOP_ARMCA35PLL_600M 133#define CLK_TOP_ARMCA35PLL_400M 234#define CLK_TOP_ARMCA72PLL 335#define CLK_TOP_SYSPLL 436#define CLK_TOP_SYSPLL_D2 537#define CLK_TOP_SYSPLL1_D2 638#define CLK_TOP_SYSPLL1_D4 739#define CLK_TOP_SYSPLL1_D8 840#define CLK_TOP_SYSPLL1_D16 941#define CLK_TOP_SYSPLL_D3 1042#define CLK_TOP_SYSPLL2_D2 1143#define CLK_TOP_SYSPLL2_D4 1244#define CLK_TOP_SYSPLL_D5 1345#define CLK_TOP_SYSPLL3_D2 1446#define CLK_TOP_SYSPLL3_D4 1547#define CLK_TOP_SYSPLL_D7 1648#define CLK_TOP_SYSPLL4_D2 1749#define CLK_TOP_SYSPLL4_D4 1850#define CLK_TOP_UNIVPLL 1951#define CLK_TOP_UNIVPLL_D7 2052#define CLK_TOP_UNIVPLL_D26 2153#define CLK_TOP_UNIVPLL_D52 2254#define CLK_TOP_UNIVPLL_D104 2355#define CLK_TOP_UNIVPLL_D208 2456#define CLK_TOP_UNIVPLL_D2 2557#define CLK_TOP_UNIVPLL1_D2 2658#define CLK_TOP_UNIVPLL1_D4 2759#define CLK_TOP_UNIVPLL1_D8 2860#define CLK_TOP_UNIVPLL_D3 2961#define CLK_TOP_UNIVPLL2_D2 3062#define CLK_TOP_UNIVPLL2_D4 3163#define CLK_TOP_UNIVPLL2_D8 3264#define CLK_TOP_UNIVPLL_D5 3365#define CLK_TOP_UNIVPLL3_D2 3466#define CLK_TOP_UNIVPLL3_D4 3567#define CLK_TOP_UNIVPLL3_D8 3668#define CLK_TOP_F_MP0_PLL1 3769#define CLK_TOP_F_MP0_PLL2 3870#define CLK_TOP_F_BIG_PLL1 3971#define CLK_TOP_F_BIG_PLL2 4072#define CLK_TOP_F_BUS_PLL1 4173#define CLK_TOP_F_BUS_PLL2 4274#define CLK_TOP_APLL1 4375#define CLK_TOP_APLL1_D2 4476#define CLK_TOP_APLL1_D4 4577#define CLK_TOP_APLL1_D8 4678#define CLK_TOP_APLL1_D16 4779#define CLK_TOP_APLL2 4880#define CLK_TOP_APLL2_D2 4981#define CLK_TOP_APLL2_D4 5082#define CLK_TOP_APLL2_D8 5183#define CLK_TOP_APLL2_D16 5284#define CLK_TOP_LVDSPLL 5385#define CLK_TOP_LVDSPLL_D2 5486#define CLK_TOP_LVDSPLL_D4 5587#define CLK_TOP_LVDSPLL_D8 5688#define CLK_TOP_LVDSPLL2 5789#define CLK_TOP_LVDSPLL2_D2 5890#define CLK_TOP_LVDSPLL2_D4 5991#define CLK_TOP_LVDSPLL2_D8 6092#define CLK_TOP_ETHERPLL_125M 6193#define CLK_TOP_ETHERPLL_50M 6294#define CLK_TOP_CVBS 6395#define CLK_TOP_CVBS_D2 6496#define CLK_TOP_SYS_26M 6597#define CLK_TOP_MMPLL 6698#define CLK_TOP_MMPLL_D2 6799#define CLK_TOP_VENCPLL 68100#define CLK_TOP_VENCPLL_D2 69101#define CLK_TOP_VCODECPLL 70102#define CLK_TOP_VCODECPLL_D2 71103#define CLK_TOP_TVDPLL 72104#define CLK_TOP_TVDPLL_D2 73105#define CLK_TOP_TVDPLL_D4 74106#define CLK_TOP_TVDPLL_D8 75107#define CLK_TOP_TVDPLL_429M 76108#define CLK_TOP_TVDPLL_429M_D2 77109#define CLK_TOP_TVDPLL_429M_D4 78110#define CLK_TOP_MSDCPLL 79111#define CLK_TOP_MSDCPLL_D2 80112#define CLK_TOP_MSDCPLL_D4 81113#define CLK_TOP_MSDCPLL2 82114#define CLK_TOP_MSDCPLL2_D2 83115#define CLK_TOP_MSDCPLL2_D4 84116#define CLK_TOP_CLK26M_D2 85117#define CLK_TOP_D2A_ULCLK_6P5M 86118#define CLK_TOP_VPLL3_DPIX 87119#define CLK_TOP_VPLL_DPIX 88120#define CLK_TOP_LTEPLL_FS26M 89121#define CLK_TOP_DMPLL 90122#define CLK_TOP_DSI0_LNTC 91123#define CLK_TOP_DSI1_LNTC 92124#define CLK_TOP_LVDSTX3_CLKDIG_CTS 93125#define CLK_TOP_LVDSTX_CLKDIG_CTS 94126#define CLK_TOP_CLKRTC_EXT 95127#define CLK_TOP_CLKRTC_INT 96128#define CLK_TOP_CSI0 97129#define CLK_TOP_CVBSPLL 98130#define CLK_TOP_AXI_SEL 99131#define CLK_TOP_MEM_SEL 100132#define CLK_TOP_MM_SEL 101133#define CLK_TOP_PWM_SEL 102134#define CLK_TOP_VDEC_SEL 103135#define CLK_TOP_VENC_SEL 104136#define CLK_TOP_MFG_SEL 105137#define CLK_TOP_CAMTG_SEL 106138#define CLK_TOP_UART_SEL 107139#define CLK_TOP_SPI_SEL 108140#define CLK_TOP_USB20_SEL 109141#define CLK_TOP_USB30_SEL 110142#define CLK_TOP_MSDC50_0_HCLK_SEL 111143#define CLK_TOP_MSDC50_0_SEL 112144#define CLK_TOP_MSDC30_1_SEL 113145#define CLK_TOP_MSDC30_2_SEL 114146#define CLK_TOP_MSDC30_3_SEL 115147#define CLK_TOP_AUDIO_SEL 116148#define CLK_TOP_AUD_INTBUS_SEL 117149#define CLK_TOP_PMICSPI_SEL 118150#define CLK_TOP_DPILVDS1_SEL 119151#define CLK_TOP_ATB_SEL 120152#define CLK_TOP_NR_SEL 121153#define CLK_TOP_NFI2X_SEL 122154#define CLK_TOP_IRDA_SEL 123155#define CLK_TOP_CCI400_SEL 124156#define CLK_TOP_AUD_1_SEL 125157#define CLK_TOP_AUD_2_SEL 126158#define CLK_TOP_MEM_MFG_IN_AS_SEL 127159#define CLK_TOP_AXI_MFG_IN_AS_SEL 128160#define CLK_TOP_SCAM_SEL 129161#define CLK_TOP_NFIECC_SEL 130162#define CLK_TOP_PE2_MAC_P0_SEL 131163#define CLK_TOP_PE2_MAC_P1_SEL 132164#define CLK_TOP_DPILVDS_SEL 133165#define CLK_TOP_MSDC50_3_HCLK_SEL 134166#define CLK_TOP_HDCP_SEL 135167#define CLK_TOP_HDCP_24M_SEL 136168#define CLK_TOP_RTC_SEL 137169#define CLK_TOP_SPINOR_SEL 138170#define CLK_TOP_APLL_SEL 139171#define CLK_TOP_APLL2_SEL 140172#define CLK_TOP_A1SYS_HP_SEL 141173#define CLK_TOP_A2SYS_HP_SEL 142174#define CLK_TOP_ASM_L_SEL 143175#define CLK_TOP_ASM_M_SEL 144176#define CLK_TOP_ASM_H_SEL 145177#define CLK_TOP_I2SO1_SEL 146178#define CLK_TOP_I2SO2_SEL 147179#define CLK_TOP_I2SO3_SEL 148180#define CLK_TOP_TDMO0_SEL 149181#define CLK_TOP_TDMO1_SEL 150182#define CLK_TOP_I2SI1_SEL 151183#define CLK_TOP_I2SI2_SEL 152184#define CLK_TOP_I2SI3_SEL 153185#define CLK_TOP_ETHER_125M_SEL 154186#define CLK_TOP_ETHER_50M_SEL 155187#define CLK_TOP_JPGDEC_SEL 156188#define CLK_TOP_SPISLV_SEL 157189#define CLK_TOP_ETHER_50M_RMII_SEL 158190#define CLK_TOP_CAM2TG_SEL 159191#define CLK_TOP_DI_SEL 160192#define CLK_TOP_TVD_SEL 161193#define CLK_TOP_I2C_SEL 162194#define CLK_TOP_PWM_INFRA_SEL 163195#define CLK_TOP_MSDC0P_AES_SEL 164196#define CLK_TOP_CMSYS_SEL 165197#define CLK_TOP_GCPU_SEL 166198#define CLK_TOP_AUD_APLL1_SEL 167199#define CLK_TOP_AUD_APLL2_SEL 168200#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169201#define CLK_TOP_APLL_DIV0 170202#define CLK_TOP_APLL_DIV1 171203#define CLK_TOP_APLL_DIV2 172204#define CLK_TOP_APLL_DIV3 173205#define CLK_TOP_APLL_DIV4 174206#define CLK_TOP_APLL_DIV5 175207#define CLK_TOP_APLL_DIV6 176208#define CLK_TOP_APLL_DIV7 177209#define CLK_TOP_APLL_DIV_PDN0 178210#define CLK_TOP_APLL_DIV_PDN1 179211#define CLK_TOP_APLL_DIV_PDN2 180212#define CLK_TOP_APLL_DIV_PDN3 181213#define CLK_TOP_APLL_DIV_PDN4 182214#define CLK_TOP_APLL_DIV_PDN5 183215#define CLK_TOP_APLL_DIV_PDN6 184216#define CLK_TOP_APLL_DIV_PDN7 185217#define CLK_TOP_APLL1_D3 186218#define CLK_TOP_APLL1_REF_SEL 187219#define CLK_TOP_APLL2_REF_SEL 188220#define CLK_TOP_NFI2X_EN 189221#define CLK_TOP_NFIECC_EN 190222#define CLK_TOP_NFI1X_CK_EN 191223#define CLK_TOP_APLL2_D3 192224#define CLK_TOP_NR_CLK 193225 226/* INFRACFG */227 228#define CLK_INFRA_DBGCLK 0229#define CLK_INFRA_GCE 1230#define CLK_INFRA_M4U 2231#define CLK_INFRA_KP 3232#define CLK_INFRA_AO_SPI0 4233#define CLK_INFRA_AO_SPI1 5234#define CLK_INFRA_AO_UART5 6235#define CLK_INFRA_NR_CLK 7236 237/* PERICFG */238 239#define CLK_PERI_NFI 0240#define CLK_PERI_THERM 1241#define CLK_PERI_PWM0 2242#define CLK_PERI_PWM1 3243#define CLK_PERI_PWM2 4244#define CLK_PERI_PWM3 5245#define CLK_PERI_PWM4 6246#define CLK_PERI_PWM5 7247#define CLK_PERI_PWM6 8248#define CLK_PERI_PWM7 9249#define CLK_PERI_PWM 10250#define CLK_PERI_AP_DMA 11251#define CLK_PERI_MSDC30_0 12252#define CLK_PERI_MSDC30_1 13253#define CLK_PERI_MSDC30_2 14254#define CLK_PERI_MSDC30_3 15255#define CLK_PERI_UART0 16256#define CLK_PERI_UART1 17257#define CLK_PERI_UART2 18258#define CLK_PERI_UART3 19259#define CLK_PERI_I2C0 20260#define CLK_PERI_I2C1 21261#define CLK_PERI_I2C2 22262#define CLK_PERI_I2C3 23263#define CLK_PERI_I2C4 24264#define CLK_PERI_AUXADC 25265#define CLK_PERI_SPI0 26266#define CLK_PERI_SPI 27267#define CLK_PERI_I2C5 28268#define CLK_PERI_SPI2 29269#define CLK_PERI_SPI3 30270#define CLK_PERI_SPI5 31271#define CLK_PERI_UART4 32272#define CLK_PERI_SFLASH 33273#define CLK_PERI_GMAC 34274#define CLK_PERI_PCIE0 35275#define CLK_PERI_PCIE1 36276#define CLK_PERI_GMAC_PCLK 37277#define CLK_PERI_MSDC50_0_EN 38278#define CLK_PERI_MSDC30_1_EN 39279#define CLK_PERI_MSDC30_2_EN 40280#define CLK_PERI_MSDC30_3_EN 41281#define CLK_PERI_MSDC50_0_HCLK_EN 42282#define CLK_PERI_MSDC50_3_HCLK_EN 43283#define CLK_PERI_MSDC30_0_QTR_EN 44284#define CLK_PERI_MSDC30_3_QTR_EN 45285#define CLK_PERI_NR_CLK 46286 287/* MCUCFG */288 289#define CLK_MCU_MP0_SEL 0290#define CLK_MCU_MP2_SEL 1291#define CLK_MCU_BUS_SEL 2292#define CLK_MCU_NR_CLK 3293 294/* MFGCFG */295 296#define CLK_MFG_BG3D 0297#define CLK_MFG_NR_CLK 1298 299/* MMSYS */300 301#define CLK_MM_SMI_COMMON 0302#define CLK_MM_SMI_LARB0 1303#define CLK_MM_CAM_MDP 2304#define CLK_MM_MDP_RDMA0 3305#define CLK_MM_MDP_RDMA1 4306#define CLK_MM_MDP_RSZ0 5307#define CLK_MM_MDP_RSZ1 6308#define CLK_MM_MDP_RSZ2 7309#define CLK_MM_MDP_TDSHP0 8310#define CLK_MM_MDP_TDSHP1 9311#define CLK_MM_MDP_CROP 10312#define CLK_MM_MDP_WDMA 11313#define CLK_MM_MDP_WROT0 12314#define CLK_MM_MDP_WROT1 13315#define CLK_MM_FAKE_ENG 14316#define CLK_MM_MUTEX_32K 15317#define CLK_MM_DISP_OVL0 16318#define CLK_MM_DISP_OVL1 17319#define CLK_MM_DISP_RDMA0 18320#define CLK_MM_DISP_RDMA1 19321#define CLK_MM_DISP_RDMA2 20322#define CLK_MM_DISP_WDMA0 21323#define CLK_MM_DISP_WDMA1 22324#define CLK_MM_DISP_COLOR0 23325#define CLK_MM_DISP_COLOR1 24326#define CLK_MM_DISP_AAL 25327#define CLK_MM_DISP_GAMMA 26328#define CLK_MM_DISP_UFOE 27329#define CLK_MM_DISP_SPLIT0 28330#define CLK_MM_DISP_OD 29331#define CLK_MM_DISP_PWM0_MM 30332#define CLK_MM_DISP_PWM0_26M 31333#define CLK_MM_DISP_PWM1_MM 32334#define CLK_MM_DISP_PWM1_26M 33335#define CLK_MM_DSI0_ENGINE 34336#define CLK_MM_DSI0_DIGITAL 35337#define CLK_MM_DSI1_ENGINE 36338#define CLK_MM_DSI1_DIGITAL 37339#define CLK_MM_DPI_PIXEL 38340#define CLK_MM_DPI_ENGINE 39341#define CLK_MM_DPI1_PIXEL 40342#define CLK_MM_DPI1_ENGINE 41343#define CLK_MM_LVDS_PIXEL 42344#define CLK_MM_LVDS_CTS 43345#define CLK_MM_SMI_LARB4 44346#define CLK_MM_SMI_COMMON1 45347#define CLK_MM_SMI_LARB5 46348#define CLK_MM_MDP_RDMA2 47349#define CLK_MM_MDP_TDSHP2 48350#define CLK_MM_DISP_OVL2 49351#define CLK_MM_DISP_WDMA2 50352#define CLK_MM_DISP_COLOR2 51353#define CLK_MM_DISP_AAL1 52354#define CLK_MM_DISP_OD1 53355#define CLK_MM_LVDS1_PIXEL 54356#define CLK_MM_LVDS1_CTS 55357#define CLK_MM_SMI_LARB7 56358#define CLK_MM_MDP_RDMA3 57359#define CLK_MM_MDP_WROT2 58360#define CLK_MM_DSI2 59361#define CLK_MM_DSI2_DIGITAL 60362#define CLK_MM_DSI3 61363#define CLK_MM_DSI3_DIGITAL 62364#define CLK_MM_NR_CLK 63365 366/* IMGSYS */367 368#define CLK_IMG_SMI_LARB2 0369#define CLK_IMG_SENINF_SCAM_EN 1370#define CLK_IMG_SENINF_CAM_EN 2371#define CLK_IMG_CAM_SV_EN 3372#define CLK_IMG_CAM_SV1_EN 4373#define CLK_IMG_CAM_SV2_EN 5374#define CLK_IMG_NR_CLK 6375 376/* BDPSYS */377 378#define CLK_BDP_BRIDGE_B 0379#define CLK_BDP_BRIDGE_DRAM 1380#define CLK_BDP_LARB_DRAM 2381#define CLK_BDP_WR_CHANNEL_VDI_PXL 3382#define CLK_BDP_WR_CHANNEL_VDI_DRAM 4383#define CLK_BDP_WR_CHANNEL_VDI_B 5384#define CLK_BDP_MT_B 6385#define CLK_BDP_DISPFMT_27M 7386#define CLK_BDP_DISPFMT_27M_VDOUT 8387#define CLK_BDP_DISPFMT_27_74_74 9388#define CLK_BDP_DISPFMT_2FS 10389#define CLK_BDP_DISPFMT_2FS_2FS74_148 11390#define CLK_BDP_DISPFMT_B 12391#define CLK_BDP_VDO_DRAM 13392#define CLK_BDP_VDO_2FS 14393#define CLK_BDP_VDO_B 15394#define CLK_BDP_WR_CHANNEL_DI_PXL 16395#define CLK_BDP_WR_CHANNEL_DI_DRAM 17396#define CLK_BDP_WR_CHANNEL_DI_B 18397#define CLK_BDP_NR_AGENT 19398#define CLK_BDP_NR_DRAM 20399#define CLK_BDP_NR_B 21400#define CLK_BDP_BRIDGE_RT_B 22401#define CLK_BDP_BRIDGE_RT_DRAM 23402#define CLK_BDP_LARB_RT_DRAM 24403#define CLK_BDP_TVD_TDC 25404#define CLK_BDP_TVD_54 26405#define CLK_BDP_TVD_CBUS 27406#define CLK_BDP_NR_CLK 28407 408/* VDECSYS */409 410#define CLK_VDEC_CKEN 0411#define CLK_VDEC_LARB1_CKEN 1412#define CLK_VDEC_IMGRZ_CKEN 2413#define CLK_VDEC_NR_CLK 3414 415/* VENCSYS */416 417#define CLK_VENC_SMI_COMMON_CON 0418#define CLK_VENC_VENC 1419#define CLK_VENC_SMI_LARB6 2420#define CLK_VENC_NR_CLK 3421 422/* JPGDECSYS */423 424#define CLK_JPGDEC_JPGDEC1 0425#define CLK_JPGDEC_JPGDEC 1426#define CLK_JPGDEC_NR_CLK 2427 428#endif /* _DT_BINDINGS_CLK_MT2712_H */429