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1/* SPDX-License-Identifier: GPL-2.0 */2 3#ifndef _DT_BINDINGS_CLK_MT6765_H4#define _DT_BINDINGS_CLK_MT6765_H5 6/* FIX Clks */7#define CLK_TOP_CLK26M 08 9/* APMIXEDSYS */10#define CLK_APMIXED_ARMPLL_L 011#define CLK_APMIXED_ARMPLL 112#define CLK_APMIXED_CCIPLL 213#define CLK_APMIXED_MAINPLL 314#define CLK_APMIXED_MFGPLL 415#define CLK_APMIXED_MMPLL 516#define CLK_APMIXED_UNIV2PLL 617#define CLK_APMIXED_MSDCPLL 718#define CLK_APMIXED_APLL1 819#define CLK_APMIXED_MPLL 920#define CLK_APMIXED_ULPOSC1 1021#define CLK_APMIXED_ULPOSC2 1122#define CLK_APMIXED_SSUSB26M 1223#define CLK_APMIXED_APPLL26M 1324#define CLK_APMIXED_MIPIC0_26M 1425#define CLK_APMIXED_MDPLLGP26M 1526#define CLK_APMIXED_MMSYS_F26M 1627#define CLK_APMIXED_UFS26M 1728#define CLK_APMIXED_MIPIC1_26M 1829#define CLK_APMIXED_MEMPLL26M 1930#define CLK_APMIXED_CLKSQ_LVPLL_26M 2031#define CLK_APMIXED_MIPID0_26M 2132#define CLK_APMIXED_NR_CLK 2233 34/* TOPCKGEN */35#define CLK_TOP_SYSPLL 036#define CLK_TOP_SYSPLL_D2 137#define CLK_TOP_SYSPLL1_D2 238#define CLK_TOP_SYSPLL1_D4 339#define CLK_TOP_SYSPLL1_D8 440#define CLK_TOP_SYSPLL1_D16 541#define CLK_TOP_SYSPLL_D3 642#define CLK_TOP_SYSPLL2_D2 743#define CLK_TOP_SYSPLL2_D4 844#define CLK_TOP_SYSPLL2_D8 945#define CLK_TOP_SYSPLL_D5 1046#define CLK_TOP_SYSPLL3_D2 1147#define CLK_TOP_SYSPLL3_D4 1248#define CLK_TOP_SYSPLL_D7 1349#define CLK_TOP_SYSPLL4_D2 1450#define CLK_TOP_SYSPLL4_D4 1551#define CLK_TOP_USB20_192M 1652#define CLK_TOP_USB20_192M_D4 1753#define CLK_TOP_USB20_192M_D8 1854#define CLK_TOP_USB20_192M_D16 1955#define CLK_TOP_USB20_192M_D32 2056#define CLK_TOP_UNIVPLL 2157#define CLK_TOP_UNIVPLL_D2 2258#define CLK_TOP_UNIVPLL1_D2 2359#define CLK_TOP_UNIVPLL1_D4 2460#define CLK_TOP_UNIVPLL_D3 2561#define CLK_TOP_UNIVPLL2_D2 2662#define CLK_TOP_UNIVPLL2_D4 2763#define CLK_TOP_UNIVPLL2_D8 2864#define CLK_TOP_UNIVPLL2_D32 2965#define CLK_TOP_UNIVPLL_D5 3066#define CLK_TOP_UNIVPLL3_D2 3167#define CLK_TOP_UNIVPLL3_D4 3268#define CLK_TOP_MMPLL 3369#define CLK_TOP_MMPLL_D2 3470#define CLK_TOP_MPLL 3571#define CLK_TOP_DA_MPLL_104M_DIV 3672#define CLK_TOP_DA_MPLL_52M_DIV 3773#define CLK_TOP_MFGPLL 3874#define CLK_TOP_MSDCPLL 3975#define CLK_TOP_MSDCPLL_D2 4076#define CLK_TOP_APLL1 4177#define CLK_TOP_APLL1_D2 4278#define CLK_TOP_APLL1_D4 4379#define CLK_TOP_APLL1_D8 4480#define CLK_TOP_ULPOSC1 4581#define CLK_TOP_ULPOSC1_D2 4682#define CLK_TOP_ULPOSC1_D4 4783#define CLK_TOP_ULPOSC1_D8 4884#define CLK_TOP_ULPOSC1_D16 4985#define CLK_TOP_ULPOSC1_D32 5086#define CLK_TOP_DMPLL 5187#define CLK_TOP_F_FRTC 5288#define CLK_TOP_F_F26M 5389#define CLK_TOP_AXI 5490#define CLK_TOP_MM 5591#define CLK_TOP_SCP 5692#define CLK_TOP_MFG 5793#define CLK_TOP_F_FUART 5894#define CLK_TOP_SPI 5995#define CLK_TOP_MSDC50_0 6096#define CLK_TOP_MSDC30_1 6197#define CLK_TOP_AUDIO 6298#define CLK_TOP_AUD_1 6399#define CLK_TOP_AUD_ENGEN1 64100#define CLK_TOP_F_FDISP_PWM 65101#define CLK_TOP_SSPM 66102#define CLK_TOP_DXCC 67103#define CLK_TOP_I2C 68104#define CLK_TOP_F_FPWM 69105#define CLK_TOP_F_FSENINF 70106#define CLK_TOP_AES_FDE 71107#define CLK_TOP_F_BIST2FPC 72108#define CLK_TOP_ARMPLL_DIVIDER_PLL0 73109#define CLK_TOP_ARMPLL_DIVIDER_PLL1 74110#define CLK_TOP_ARMPLL_DIVIDER_PLL2 75111#define CLK_TOP_DA_USB20_48M_DIV 76112#define CLK_TOP_DA_UNIV_48M_DIV 77113#define CLK_TOP_APLL12_DIV0 78114#define CLK_TOP_APLL12_DIV1 79115#define CLK_TOP_APLL12_DIV2 80116#define CLK_TOP_APLL12_DIV3 81117#define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN 82118#define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN 83119#define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN 84120#define CLK_TOP_FMEM_OCC_DRC_EN 85121#define CLK_TOP_USB20_48M_EN 86122#define CLK_TOP_UNIVPLL_48M_EN 87123#define CLK_TOP_MPLL_104M_EN 88124#define CLK_TOP_MPLL_52M_EN 89125#define CLK_TOP_F_UFS_MP_SAP_CFG_EN 90126#define CLK_TOP_F_BIST2FPC_EN 91127#define CLK_TOP_MD_32K 92128#define CLK_TOP_MD_26M 93129#define CLK_TOP_MD2_32K 94130#define CLK_TOP_MD2_26M 95131#define CLK_TOP_AXI_SEL 96132#define CLK_TOP_MEM_SEL 97133#define CLK_TOP_MM_SEL 98134#define CLK_TOP_SCP_SEL 99135#define CLK_TOP_MFG_SEL 100136#define CLK_TOP_ATB_SEL 101137#define CLK_TOP_CAMTG_SEL 102138#define CLK_TOP_CAMTG1_SEL 103139#define CLK_TOP_CAMTG2_SEL 104140#define CLK_TOP_CAMTG3_SEL 105141#define CLK_TOP_UART_SEL 106142#define CLK_TOP_SPI_SEL 107143#define CLK_TOP_MSDC50_0_HCLK_SEL 108144#define CLK_TOP_MSDC50_0_SEL 109145#define CLK_TOP_MSDC30_1_SEL 110146#define CLK_TOP_AUDIO_SEL 111147#define CLK_TOP_AUD_INTBUS_SEL 112148#define CLK_TOP_AUD_1_SEL 113149#define CLK_TOP_AUD_ENGEN1_SEL 114150#define CLK_TOP_DISP_PWM_SEL 115151#define CLK_TOP_SSPM_SEL 116152#define CLK_TOP_DXCC_SEL 117153#define CLK_TOP_USB_TOP_SEL 118154#define CLK_TOP_SPM_SEL 119155#define CLK_TOP_I2C_SEL 120156#define CLK_TOP_PWM_SEL 121157#define CLK_TOP_SENINF_SEL 122158#define CLK_TOP_AES_FDE_SEL 123159#define CLK_TOP_PWRAP_ULPOSC_SEL 124160#define CLK_TOP_CAMTM_SEL 125161#define CLK_TOP_NR_CLK 126162 163/* INFRACFG */164#define CLK_IFR_ICUSB 0165#define CLK_IFR_GCE 1166#define CLK_IFR_THERM 2167#define CLK_IFR_I2C_AP 3168#define CLK_IFR_I2C_CCU 4169#define CLK_IFR_I2C_SSPM 5170#define CLK_IFR_I2C_RSV 6171#define CLK_IFR_PWM_HCLK 7172#define CLK_IFR_PWM1 8173#define CLK_IFR_PWM2 9174#define CLK_IFR_PWM3 10175#define CLK_IFR_PWM4 11176#define CLK_IFR_PWM5 12177#define CLK_IFR_PWM 13178#define CLK_IFR_UART0 14179#define CLK_IFR_UART1 15180#define CLK_IFR_GCE_26M 16181#define CLK_IFR_CQ_DMA_FPC 17182#define CLK_IFR_BTIF 18183#define CLK_IFR_SPI0 19184#define CLK_IFR_MSDC0 20185#define CLK_IFR_MSDC1 21186#define CLK_IFR_TRNG 22187#define CLK_IFR_AUXADC 23188#define CLK_IFR_CCIF1_AP 24189#define CLK_IFR_CCIF1_MD 25190#define CLK_IFR_AUXADC_MD 26191#define CLK_IFR_AP_DMA 27192#define CLK_IFR_DEVICE_APC 28193#define CLK_IFR_CCIF_AP 29194#define CLK_IFR_AUDIO 30195#define CLK_IFR_CCIF_MD 31196#define CLK_IFR_RG_PWM_FBCLK6 32197#define CLK_IFR_DISP_PWM 33198#define CLK_IFR_CLDMA_BCLK 34199#define CLK_IFR_AUDIO_26M_BCLK 35200#define CLK_IFR_SPI1 36201#define CLK_IFR_I2C4 37202#define CLK_IFR_SPI2 38203#define CLK_IFR_SPI3 39204#define CLK_IFR_I2C5 40205#define CLK_IFR_I2C5_ARBITER 41206#define CLK_IFR_I2C5_IMM 42207#define CLK_IFR_I2C1_ARBITER 43208#define CLK_IFR_I2C1_IMM 44209#define CLK_IFR_I2C2_ARBITER 45210#define CLK_IFR_I2C2_IMM 46211#define CLK_IFR_SPI4 47212#define CLK_IFR_SPI5 48213#define CLK_IFR_CQ_DMA 49214#define CLK_IFR_FAES_FDE 50215#define CLK_IFR_MSDC0_SELF 51216#define CLK_IFR_MSDC1_SELF 52217#define CLK_IFR_I2C6 53218#define CLK_IFR_AP_MSDC0 54219#define CLK_IFR_MD_MSDC0 55220#define CLK_IFR_MSDC0_SRC 56221#define CLK_IFR_MSDC1_SRC 57222#define CLK_IFR_AES_TOP0_BCLK 58223#define CLK_IFR_MCU_PM_BCLK 59224#define CLK_IFR_CCIF2_AP 60225#define CLK_IFR_CCIF2_MD 61226#define CLK_IFR_CCIF3_AP 62227#define CLK_IFR_CCIF3_MD 63228#define CLK_IFR_NR_CLK 64229 230/* AUDIO */231#define CLK_AUDIO_AFE 0232#define CLK_AUDIO_22M 1233#define CLK_AUDIO_APLL_TUNER 2234#define CLK_AUDIO_ADC 3235#define CLK_AUDIO_DAC 4236#define CLK_AUDIO_DAC_PREDIS 5237#define CLK_AUDIO_TML 6238#define CLK_AUDIO_I2S1_BCLK 7239#define CLK_AUDIO_I2S2_BCLK 8240#define CLK_AUDIO_I2S3_BCLK 9241#define CLK_AUDIO_I2S4_BCLK 10242#define CLK_AUDIO_NR_CLK 11243 244/* MIPI_RX_ANA_CSI0A */245 246#define CLK_MIPI0A_CSR_CSI_EN_0A 0247#define CLK_MIPI0A_NR_CLK 1248 249/* MMSYS_CONFIG */250 251#define CLK_MM_MDP_RDMA0 0252#define CLK_MM_MDP_CCORR0 1253#define CLK_MM_MDP_RSZ0 2254#define CLK_MM_MDP_RSZ1 3255#define CLK_MM_MDP_TDSHP0 4256#define CLK_MM_MDP_WROT0 5257#define CLK_MM_MDP_WDMA0 6258#define CLK_MM_DISP_OVL0 7259#define CLK_MM_DISP_OVL0_2L 8260#define CLK_MM_DISP_RSZ0 9261#define CLK_MM_DISP_RDMA0 10262#define CLK_MM_DISP_WDMA0 11263#define CLK_MM_DISP_COLOR0 12264#define CLK_MM_DISP_CCORR0 13265#define CLK_MM_DISP_AAL0 14266#define CLK_MM_DISP_GAMMA0 15267#define CLK_MM_DISP_DITHER0 16268#define CLK_MM_DSI0 17269#define CLK_MM_FAKE_ENG 18270#define CLK_MM_SMI_COMMON 19271#define CLK_MM_SMI_LARB0 20272#define CLK_MM_SMI_COMM0 21273#define CLK_MM_SMI_COMM1 22274#define CLK_MM_CAM_MDP 23275#define CLK_MM_SMI_IMG 24276#define CLK_MM_SMI_CAM 25277#define CLK_MM_IMG_DL_RELAY 26278#define CLK_MM_IMG_DL_ASYNC_TOP 27279#define CLK_MM_DIG_DSI 28280#define CLK_MM_F26M_HRTWT 29281#define CLK_MM_NR_CLK 30282 283/* IMGSYS */284 285#define CLK_IMG_LARB2 0286#define CLK_IMG_DIP 1287#define CLK_IMG_FDVT 2288#define CLK_IMG_DPE 3289#define CLK_IMG_RSC 4290#define CLK_IMG_NR_CLK 5291 292/* VENCSYS */293 294#define CLK_VENC_SET0_LARB 0295#define CLK_VENC_SET1_VENC 1296#define CLK_VENC_SET2_JPGENC 2297#define CLK_VENC_SET3_VDEC 3298#define CLK_VENC_NR_CLK 4299 300/* CAMSYS */301 302#define CLK_CAM_LARB3 0303#define CLK_CAM_DFP_VAD 1304#define CLK_CAM 2305#define CLK_CAMTG 3306#define CLK_CAM_SENINF 4307#define CLK_CAMSV0 5308#define CLK_CAMSV1 6309#define CLK_CAMSV2 7310#define CLK_CAM_CCU 8311#define CLK_CAM_NR_CLK 9312 313#endif /* _DT_BINDINGS_CLK_MT6765_H */314