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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2019 MediaTek Inc.4 * Author: Wendell Lin <wendell.lin@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_CLK_MT6779_H8#define _DT_BINDINGS_CLK_MT6779_H9 10/* TOPCKGEN */11#define CLK_TOP_AXI 112#define CLK_TOP_MM 213#define CLK_TOP_CAM 314#define CLK_TOP_MFG 415#define CLK_TOP_CAMTG 516#define CLK_TOP_UART 617#define CLK_TOP_SPI 718#define CLK_TOP_MSDC50_0_HCLK 819#define CLK_TOP_MSDC50_0 920#define CLK_TOP_MSDC30_1 1021#define CLK_TOP_MSDC30_2 1122#define CLK_TOP_AUD 1223#define CLK_TOP_AUD_INTBUS 1324#define CLK_TOP_FPWRAP_ULPOSC 1425#define CLK_TOP_SCP 1526#define CLK_TOP_ATB 1627#define CLK_TOP_SSPM 1728#define CLK_TOP_DPI0 1829#define CLK_TOP_SCAM 1930#define CLK_TOP_AUD_1 2031#define CLK_TOP_AUD_2 2132#define CLK_TOP_DISP_PWM 2233#define CLK_TOP_SSUSB_TOP_XHCI 2334#define CLK_TOP_USB_TOP 2435#define CLK_TOP_SPM 2536#define CLK_TOP_I2C 2637#define CLK_TOP_F52M_MFG 2738#define CLK_TOP_SENINF 2839#define CLK_TOP_DXCC 2940#define CLK_TOP_CAMTG2 3041#define CLK_TOP_AUD_ENG1 3142#define CLK_TOP_AUD_ENG2 3243#define CLK_TOP_FAES_UFSFDE 3344#define CLK_TOP_FUFS 3445#define CLK_TOP_IMG 3546#define CLK_TOP_DSP 3647#define CLK_TOP_DSP1 3748#define CLK_TOP_DSP2 3849#define CLK_TOP_IPU_IF 3950#define CLK_TOP_CAMTG3 4051#define CLK_TOP_CAMTG4 4152#define CLK_TOP_PMICSPI 4253#define CLK_TOP_MAINPLL_CK 4354#define CLK_TOP_MAINPLL_D2 4455#define CLK_TOP_MAINPLL_D3 4556#define CLK_TOP_MAINPLL_D5 4657#define CLK_TOP_MAINPLL_D7 4758#define CLK_TOP_MAINPLL_D2_D2 4859#define CLK_TOP_MAINPLL_D2_D4 4960#define CLK_TOP_MAINPLL_D2_D8 5061#define CLK_TOP_MAINPLL_D2_D16 5162#define CLK_TOP_MAINPLL_D3_D2 5263#define CLK_TOP_MAINPLL_D3_D4 5364#define CLK_TOP_MAINPLL_D3_D8 5465#define CLK_TOP_MAINPLL_D5_D2 5566#define CLK_TOP_MAINPLL_D5_D4 5667#define CLK_TOP_MAINPLL_D7_D2 5768#define CLK_TOP_MAINPLL_D7_D4 5869#define CLK_TOP_UNIVPLL_CK 5970#define CLK_TOP_UNIVPLL_D2 6071#define CLK_TOP_UNIVPLL_D3 6172#define CLK_TOP_UNIVPLL_D5 6273#define CLK_TOP_UNIVPLL_D7 6374#define CLK_TOP_UNIVPLL_D2_D2 6475#define CLK_TOP_UNIVPLL_D2_D4 6576#define CLK_TOP_UNIVPLL_D2_D8 6677#define CLK_TOP_UNIVPLL_D3_D2 6778#define CLK_TOP_UNIVPLL_D3_D4 6879#define CLK_TOP_UNIVPLL_D3_D8 6980#define CLK_TOP_UNIVPLL_D5_D2 7081#define CLK_TOP_UNIVPLL_D5_D4 7182#define CLK_TOP_UNIVPLL_D5_D8 7283#define CLK_TOP_APLL1_CK 7384#define CLK_TOP_APLL1_D2 7485#define CLK_TOP_APLL1_D4 7586#define CLK_TOP_APLL1_D8 7687#define CLK_TOP_APLL2_CK 7788#define CLK_TOP_APLL2_D2 7889#define CLK_TOP_APLL2_D4 7990#define CLK_TOP_APLL2_D8 8091#define CLK_TOP_TVDPLL_CK 8192#define CLK_TOP_TVDPLL_D2 8293#define CLK_TOP_TVDPLL_D4 8394#define CLK_TOP_TVDPLL_D8 8495#define CLK_TOP_TVDPLL_D16 8596#define CLK_TOP_MSDCPLL_CK 8697#define CLK_TOP_MSDCPLL_D2 8798#define CLK_TOP_MSDCPLL_D4 8899#define CLK_TOP_MSDCPLL_D8 89100#define CLK_TOP_MSDCPLL_D16 90101#define CLK_TOP_AD_OSC_CK 91102#define CLK_TOP_OSC_D2 92103#define CLK_TOP_OSC_D4 93104#define CLK_TOP_OSC_D8 94105#define CLK_TOP_OSC_D16 95106#define CLK_TOP_F26M_CK_D2 96107#define CLK_TOP_MFGPLL_CK 97108#define CLK_TOP_UNIVP_192M_CK 98109#define CLK_TOP_UNIVP_192M_D2 99110#define CLK_TOP_UNIVP_192M_D4 100111#define CLK_TOP_UNIVP_192M_D8 101112#define CLK_TOP_UNIVP_192M_D16 102113#define CLK_TOP_UNIVP_192M_D32 103114#define CLK_TOP_MMPLL_CK 104115#define CLK_TOP_MMPLL_D4 105116#define CLK_TOP_MMPLL_D4_D2 106117#define CLK_TOP_MMPLL_D4_D4 107118#define CLK_TOP_MMPLL_D5 108119#define CLK_TOP_MMPLL_D5_D2 109120#define CLK_TOP_MMPLL_D5_D4 110121#define CLK_TOP_MMPLL_D6 111122#define CLK_TOP_MMPLL_D7 112123#define CLK_TOP_CLK26M 113124#define CLK_TOP_CLK13M 114125#define CLK_TOP_ADSP 115126#define CLK_TOP_DPMAIF 116127#define CLK_TOP_VENC 117128#define CLK_TOP_VDEC 118129#define CLK_TOP_CAMTM 119130#define CLK_TOP_PWM 120131#define CLK_TOP_ADSPPLL_CK 121132#define CLK_TOP_I2S0_M_SEL 122133#define CLK_TOP_I2S1_M_SEL 123134#define CLK_TOP_I2S2_M_SEL 124135#define CLK_TOP_I2S3_M_SEL 125136#define CLK_TOP_I2S4_M_SEL 126137#define CLK_TOP_I2S5_M_SEL 127138#define CLK_TOP_APLL12_DIV0 128139#define CLK_TOP_APLL12_DIV1 129140#define CLK_TOP_APLL12_DIV2 130141#define CLK_TOP_APLL12_DIV3 131142#define CLK_TOP_APLL12_DIV4 132143#define CLK_TOP_APLL12_DIVB 133144#define CLK_TOP_APLL12_DIV5 134145#define CLK_TOP_IPE 135146#define CLK_TOP_DPE 136147#define CLK_TOP_CCU 137148#define CLK_TOP_DSP3 138149#define CLK_TOP_SENINF1 139150#define CLK_TOP_SENINF2 140151#define CLK_TOP_AUD_H 141152#define CLK_TOP_CAMTG5 142153#define CLK_TOP_TVDPLL_MAINPLL_D2_CK 143154#define CLK_TOP_AD_OSC2_CK 144155#define CLK_TOP_OSC2_D2 145156#define CLK_TOP_OSC2_D3 146157#define CLK_TOP_FMEM_466M_CK 147158#define CLK_TOP_ADSPPLL_D4 148159#define CLK_TOP_ADSPPLL_D5 149160#define CLK_TOP_ADSPPLL_D6 150161#define CLK_TOP_OSC_D10 151162#define CLK_TOP_UNIVPLL_D3_D16 152163#define CLK_TOP_NR_CLK 153164 165/* APMIXED */166#define CLK_APMIXED_ARMPLL_LL 1167#define CLK_APMIXED_ARMPLL_BL 2168#define CLK_APMIXED_ARMPLL_BB 3169#define CLK_APMIXED_CCIPLL 4170#define CLK_APMIXED_MAINPLL 5171#define CLK_APMIXED_UNIV2PLL 6172#define CLK_APMIXED_MSDCPLL 7173#define CLK_APMIXED_ADSPPLL 8174#define CLK_APMIXED_MMPLL 9175#define CLK_APMIXED_MFGPLL 10176#define CLK_APMIXED_TVDPLL 11177#define CLK_APMIXED_APLL1 12178#define CLK_APMIXED_APLL2 13179#define CLK_APMIXED_SSUSB26M 14180#define CLK_APMIXED_APPLL26M 15181#define CLK_APMIXED_MIPIC0_26M 16182#define CLK_APMIXED_MDPLLGP26M 17183#define CLK_APMIXED_MM_F26M 18184#define CLK_APMIXED_UFS26M 19185#define CLK_APMIXED_MIPIC1_26M 20186#define CLK_APMIXED_MEMPLL26M 21187#define CLK_APMIXED_CLKSQ_LVPLL_26M 22188#define CLK_APMIXED_MIPID0_26M 23189#define CLK_APMIXED_MIPID1_26M 24190#define CLK_APMIXED_NR_CLK 25191 192/* CAMSYS */193#define CLK_CAM_LARB10 1194#define CLK_CAM_DFP_VAD 2195#define CLK_CAM_LARB11 3196#define CLK_CAM_LARB9 4197#define CLK_CAM_CAM 5198#define CLK_CAM_CAMTG 6199#define CLK_CAM_SENINF 7200#define CLK_CAM_CAMSV0 8201#define CLK_CAM_CAMSV1 9202#define CLK_CAM_CAMSV2 10203#define CLK_CAM_CAMSV3 11204#define CLK_CAM_CCU 12205#define CLK_CAM_FAKE_ENG 13206#define CLK_CAM_NR_CLK 14207 208/* INFRA */209#define CLK_INFRA_PMIC_TMR 1210#define CLK_INFRA_PMIC_AP 2211#define CLK_INFRA_PMIC_MD 3212#define CLK_INFRA_PMIC_CONN 4213#define CLK_INFRA_SCPSYS 5214#define CLK_INFRA_SEJ 6215#define CLK_INFRA_APXGPT 7216#define CLK_INFRA_ICUSB 8217#define CLK_INFRA_GCE 9218#define CLK_INFRA_THERM 10219#define CLK_INFRA_I2C0 11220#define CLK_INFRA_I2C1 12221#define CLK_INFRA_I2C2 13222#define CLK_INFRA_I2C3 14223#define CLK_INFRA_PWM_HCLK 15224#define CLK_INFRA_PWM1 16225#define CLK_INFRA_PWM2 17226#define CLK_INFRA_PWM3 18227#define CLK_INFRA_PWM4 19228#define CLK_INFRA_PWM 20229#define CLK_INFRA_UART0 21230#define CLK_INFRA_UART1 22231#define CLK_INFRA_UART2 23232#define CLK_INFRA_UART3 24233#define CLK_INFRA_GCE_26M 25234#define CLK_INFRA_CQ_DMA_FPC 26235#define CLK_INFRA_BTIF 27236#define CLK_INFRA_SPI0 28237#define CLK_INFRA_MSDC0 29238#define CLK_INFRA_MSDC1 30239#define CLK_INFRA_MSDC2 31240#define CLK_INFRA_MSDC0_SCK 32241#define CLK_INFRA_DVFSRC 33242#define CLK_INFRA_GCPU 34243#define CLK_INFRA_TRNG 35244#define CLK_INFRA_AUXADC 36245#define CLK_INFRA_CPUM 37246#define CLK_INFRA_CCIF1_AP 38247#define CLK_INFRA_CCIF1_MD 39248#define CLK_INFRA_AUXADC_MD 40249#define CLK_INFRA_MSDC1_SCK 41250#define CLK_INFRA_MSDC2_SCK 42251#define CLK_INFRA_AP_DMA 43252#define CLK_INFRA_XIU 44253#define CLK_INFRA_DEVICE_APC 45254#define CLK_INFRA_CCIF_AP 46255#define CLK_INFRA_DEBUGSYS 47256#define CLK_INFRA_AUD 48257#define CLK_INFRA_CCIF_MD 49258#define CLK_INFRA_DXCC_SEC_CORE 50259#define CLK_INFRA_DXCC_AO 51260#define CLK_INFRA_DRAMC_F26M 52261#define CLK_INFRA_IRTX 53262#define CLK_INFRA_DISP_PWM 54263#define CLK_INFRA_DPMAIF_CK 55264#define CLK_INFRA_AUD_26M_BCLK 56265#define CLK_INFRA_SPI1 57266#define CLK_INFRA_I2C4 58267#define CLK_INFRA_MODEM_TEMP_SHARE 59268#define CLK_INFRA_SPI2 60269#define CLK_INFRA_SPI3 61270#define CLK_INFRA_UNIPRO_SCK 62271#define CLK_INFRA_UNIPRO_TICK 63272#define CLK_INFRA_UFS_MP_SAP_BCLK 64273#define CLK_INFRA_MD32_BCLK 65274#define CLK_INFRA_SSPM 66275#define CLK_INFRA_UNIPRO_MBIST 67276#define CLK_INFRA_SSPM_BUS_HCLK 68277#define CLK_INFRA_I2C5 69278#define CLK_INFRA_I2C5_ARBITER 70279#define CLK_INFRA_I2C5_IMM 71280#define CLK_INFRA_I2C1_ARBITER 72281#define CLK_INFRA_I2C1_IMM 73282#define CLK_INFRA_I2C2_ARBITER 74283#define CLK_INFRA_I2C2_IMM 75284#define CLK_INFRA_SPI4 76285#define CLK_INFRA_SPI5 77286#define CLK_INFRA_CQ_DMA 78287#define CLK_INFRA_UFS 79288#define CLK_INFRA_AES_UFSFDE 80289#define CLK_INFRA_UFS_TICK 81290#define CLK_INFRA_MSDC0_SELF 82291#define CLK_INFRA_MSDC1_SELF 83292#define CLK_INFRA_MSDC2_SELF 84293#define CLK_INFRA_SSPM_26M_SELF 85294#define CLK_INFRA_SSPM_32K_SELF 86295#define CLK_INFRA_UFS_AXI 87296#define CLK_INFRA_I2C6 88297#define CLK_INFRA_AP_MSDC0 89298#define CLK_INFRA_MD_MSDC0 90299#define CLK_INFRA_USB 91300#define CLK_INFRA_DEVMPU_BCLK 92301#define CLK_INFRA_CCIF2_AP 93302#define CLK_INFRA_CCIF2_MD 94303#define CLK_INFRA_CCIF3_AP 95304#define CLK_INFRA_CCIF3_MD 96305#define CLK_INFRA_SEJ_F13M 97306#define CLK_INFRA_AES_BCLK 98307#define CLK_INFRA_I2C7 99308#define CLK_INFRA_I2C8 100309#define CLK_INFRA_FBIST2FPC 101310#define CLK_INFRA_CCIF4_AP 102311#define CLK_INFRA_CCIF4_MD 103312#define CLK_INFRA_FADSP 104313#define CLK_INFRA_SSUSB_XHCI 105314#define CLK_INFRA_SPI6 106315#define CLK_INFRA_SPI7 107316#define CLK_INFRA_NR_CLK 108317 318/* MFGCFG */319#define CLK_MFGCFG_BG3D 1320#define CLK_MFGCFG_NR_CLK 2321 322/* IMG */323#define CLK_IMG_WPE_A 1324#define CLK_IMG_MFB 2325#define CLK_IMG_DIP 3326#define CLK_IMG_LARB6 4327#define CLK_IMG_LARB5 5328#define CLK_IMG_NR_CLK 6329 330/* IPE */331#define CLK_IPE_LARB7 1332#define CLK_IPE_LARB8 2333#define CLK_IPE_SMI_SUBCOM 3334#define CLK_IPE_FD 4335#define CLK_IPE_FE 5336#define CLK_IPE_RSC 6337#define CLK_IPE_DPE 7338#define CLK_IPE_NR_CLK 8339 340/* MM_CONFIG */341#define CLK_MM_SMI_COMMON 1342#define CLK_MM_SMI_LARB0 2343#define CLK_MM_SMI_LARB1 3344#define CLK_MM_GALS_COMM0 4345#define CLK_MM_GALS_COMM1 5346#define CLK_MM_GALS_CCU2MM 6347#define CLK_MM_GALS_IPU12MM 7348#define CLK_MM_GALS_IMG2MM 8349#define CLK_MM_GALS_CAM2MM 9350#define CLK_MM_GALS_IPU2MM 10351#define CLK_MM_MDP_DL_TXCK 11352#define CLK_MM_IPU_DL_TXCK 12353#define CLK_MM_MDP_RDMA0 13354#define CLK_MM_MDP_RDMA1 14355#define CLK_MM_MDP_RSZ0 15356#define CLK_MM_MDP_RSZ1 16357#define CLK_MM_MDP_TDSHP 17358#define CLK_MM_MDP_WROT0 18359#define CLK_MM_FAKE_ENG 19360#define CLK_MM_DISP_OVL0 20361#define CLK_MM_DISP_OVL0_2L 21362#define CLK_MM_DISP_OVL1_2L 22363#define CLK_MM_DISP_RDMA0 23364#define CLK_MM_DISP_RDMA1 24365#define CLK_MM_DISP_WDMA0 25366#define CLK_MM_DISP_COLOR0 26367#define CLK_MM_DISP_CCORR0 27368#define CLK_MM_DISP_AAL0 28369#define CLK_MM_DISP_GAMMA0 29370#define CLK_MM_DISP_DITHER0 30371#define CLK_MM_DISP_SPLIT 31372#define CLK_MM_DSI0_MM_CK 32373#define CLK_MM_DSI0_IF_CK 33374#define CLK_MM_DPI_MM_CK 34375#define CLK_MM_DPI_IF_CK 35376#define CLK_MM_FAKE_ENG2 36377#define CLK_MM_MDP_DL_RX_CK 37378#define CLK_MM_IPU_DL_RX_CK 38379#define CLK_MM_26M 39380#define CLK_MM_MM_R2Y 40381#define CLK_MM_DISP_RSZ 41382#define CLK_MM_MDP_WDMA0 42383#define CLK_MM_MDP_AAL 43384#define CLK_MM_MDP_HDR 44385#define CLK_MM_DBI_MM_CK 45386#define CLK_MM_DBI_IF_CK 46387#define CLK_MM_MDP_WROT1 47388#define CLK_MM_DISP_POSTMASK0 48389#define CLK_MM_DISP_HRT_BW 49390#define CLK_MM_DISP_OVL_FBDC 50391#define CLK_MM_NR_CLK 51392 393/* VDEC_GCON */394#define CLK_VDEC_VDEC 1395#define CLK_VDEC_LARB1 2396#define CLK_VDEC_GCON_NR_CLK 3397 398/* VENC_GCON */399#define CLK_VENC_GCON_LARB 1400#define CLK_VENC_GCON_VENC 2401#define CLK_VENC_GCON_JPGENC 3402#define CLK_VENC_GCON_GALS 4403#define CLK_VENC_GCON_NR_CLK 5404 405/* AUD */406#define CLK_AUD_AFE 1407#define CLK_AUD_22M 2408#define CLK_AUD_24M 3409#define CLK_AUD_APLL2_TUNER 4410#define CLK_AUD_APLL_TUNER 5411#define CLK_AUD_TDM 6412#define CLK_AUD_ADC 7413#define CLK_AUD_DAC 8414#define CLK_AUD_DAC_PREDIS 9415#define CLK_AUD_TML 10416#define CLK_AUD_NLE 11417#define CLK_AUD_I2S1_BCLK_SW 12418#define CLK_AUD_I2S2_BCLK_SW 13419#define CLK_AUD_I2S3_BCLK_SW 14420#define CLK_AUD_I2S4_BCLK_SW 15421#define CLK_AUD_I2S5_BCLK_SW 16422#define CLK_AUD_CONN_I2S_ASRC 17423#define CLK_AUD_GENERAL1_ASRC 18424#define CLK_AUD_GENERAL2_ASRC 19425#define CLK_AUD_DAC_HIRES 20426#define CLK_AUD_PDN_ADDA6_ADC 21427#define CLK_AUD_ADC_HIRES 22428#define CLK_AUD_ADC_HIRES_TML 23429#define CLK_AUD_ADDA6_ADC_HIRES 24430#define CLK_AUD_3RD_DAC 25431#define CLK_AUD_3RD_DAC_PREDIS 26432#define CLK_AUD_3RD_DAC_TML 27433#define CLK_AUD_3RD_DAC_HIRES 28434#define CLK_AUD_NR_CLK 29435 436#endif /* _DT_BINDINGS_CLK_MT6779_H */437