274 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2017 MediaTek Inc.4 * Author: Kevin Chen <kevin-cw.chen@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_CLK_MT6797_H8#define _DT_BINDINGS_CLK_MT6797_H9 10/* TOPCKGEN */11#define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE 112#define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX 213#define CLK_TOP_MUX_AXI 314#define CLK_TOP_MUX_MEM 415#define CLK_TOP_MUX_DDRPHYCFG 516#define CLK_TOP_MUX_MM 617#define CLK_TOP_MUX_PWM 718#define CLK_TOP_MUX_VDEC 819#define CLK_TOP_MUX_VENC 920#define CLK_TOP_MUX_MFG 1021#define CLK_TOP_MUX_CAMTG 1122#define CLK_TOP_MUX_UART 1223#define CLK_TOP_MUX_SPI 1324#define CLK_TOP_MUX_ULPOSC_SPI_CK_MUX 1425#define CLK_TOP_MUX_USB20 1526#define CLK_TOP_MUX_MSDC50_0_HCLK 1627#define CLK_TOP_MUX_MSDC50_0 1728#define CLK_TOP_MUX_MSDC30_1 1829#define CLK_TOP_MUX_MSDC30_2 1930#define CLK_TOP_MUX_AUDIO 2031#define CLK_TOP_MUX_AUD_INTBUS 2132#define CLK_TOP_MUX_PMICSPI 2233#define CLK_TOP_MUX_SCP 2334#define CLK_TOP_MUX_ATB 2435#define CLK_TOP_MUX_MJC 2536#define CLK_TOP_MUX_DPI0 2637#define CLK_TOP_MUX_AUD_1 2738#define CLK_TOP_MUX_AUD_2 2839#define CLK_TOP_MUX_SSUSB_TOP_SYS 2940#define CLK_TOP_MUX_SPM 3041#define CLK_TOP_MUX_BSI_SPI 3142#define CLK_TOP_MUX_AUDIO_H 3243#define CLK_TOP_MUX_ANC_MD32 3344#define CLK_TOP_MUX_MFG_52M 3445#define CLK_TOP_SYSPLL_CK 3546#define CLK_TOP_SYSPLL_D2 3647#define CLK_TOP_SYSPLL1_D2 3748#define CLK_TOP_SYSPLL1_D4 3849#define CLK_TOP_SYSPLL1_D8 3950#define CLK_TOP_SYSPLL1_D16 4051#define CLK_TOP_SYSPLL_D3 4152#define CLK_TOP_SYSPLL_D3_D3 4253#define CLK_TOP_SYSPLL2_D2 4354#define CLK_TOP_SYSPLL2_D4 4455#define CLK_TOP_SYSPLL2_D8 4556#define CLK_TOP_SYSPLL_D5 4657#define CLK_TOP_SYSPLL3_D2 4758#define CLK_TOP_SYSPLL3_D4 4859#define CLK_TOP_SYSPLL_D7 4960#define CLK_TOP_SYSPLL4_D2 5061#define CLK_TOP_SYSPLL4_D4 5162#define CLK_TOP_UNIVPLL_CK 5263#define CLK_TOP_UNIVPLL_D7 5364#define CLK_TOP_UNIVPLL_D26 5465#define CLK_TOP_SSUSB_PHY_48M_CK 5566#define CLK_TOP_USB_PHY48M_CK 5667#define CLK_TOP_UNIVPLL_D2 5768#define CLK_TOP_UNIVPLL1_D2 5869#define CLK_TOP_UNIVPLL1_D4 5970#define CLK_TOP_UNIVPLL1_D8 6071#define CLK_TOP_UNIVPLL_D3 6172#define CLK_TOP_UNIVPLL2_D2 6273#define CLK_TOP_UNIVPLL2_D4 6374#define CLK_TOP_UNIVPLL2_D8 6475#define CLK_TOP_UNIVPLL_D5 6576#define CLK_TOP_UNIVPLL3_D2 6677#define CLK_TOP_UNIVPLL3_D4 6778#define CLK_TOP_UNIVPLL3_D8 6879#define CLK_TOP_ULPOSC_CK_ORG 6980#define CLK_TOP_ULPOSC_CK 7081#define CLK_TOP_ULPOSC_D2 7182#define CLK_TOP_ULPOSC_D3 7283#define CLK_TOP_ULPOSC_D4 7384#define CLK_TOP_ULPOSC_D8 7485#define CLK_TOP_ULPOSC_D10 7586#define CLK_TOP_APLL1_CK 7687#define CLK_TOP_APLL2_CK 7788#define CLK_TOP_MFGPLL_CK 7889#define CLK_TOP_MFGPLL_D2 7990#define CLK_TOP_IMGPLL_CK 8091#define CLK_TOP_IMGPLL_D2 8192#define CLK_TOP_IMGPLL_D4 8293#define CLK_TOP_CODECPLL_CK 8394#define CLK_TOP_CODECPLL_D2 8495#define CLK_TOP_VDECPLL_CK 8596#define CLK_TOP_TVDPLL_CK 8697#define CLK_TOP_TVDPLL_D2 8798#define CLK_TOP_TVDPLL_D4 8899#define CLK_TOP_TVDPLL_D8 89100#define CLK_TOP_TVDPLL_D16 90101#define CLK_TOP_MSDCPLL_CK 91102#define CLK_TOP_MSDCPLL_D2 92103#define CLK_TOP_MSDCPLL_D4 93104#define CLK_TOP_MSDCPLL_D8 94105#define CLK_TOP_NR 95106 107/* APMIXED_SYS */108#define CLK_APMIXED_MAINPLL 1109#define CLK_APMIXED_UNIVPLL 2110#define CLK_APMIXED_MFGPLL 3111#define CLK_APMIXED_MSDCPLL 4112#define CLK_APMIXED_IMGPLL 5113#define CLK_APMIXED_TVDPLL 6114#define CLK_APMIXED_CODECPLL 7115#define CLK_APMIXED_VDECPLL 8116#define CLK_APMIXED_APLL1 9117#define CLK_APMIXED_APLL2 10118#define CLK_APMIXED_NR 11119 120/* INFRA_SYS */121#define CLK_INFRA_PMIC_TMR 1122#define CLK_INFRA_PMIC_AP 2123#define CLK_INFRA_PMIC_MD 3124#define CLK_INFRA_PMIC_CONN 4125#define CLK_INFRA_SCP 5126#define CLK_INFRA_SEJ 6127#define CLK_INFRA_APXGPT 7128#define CLK_INFRA_SEJ_13M 8129#define CLK_INFRA_ICUSB 9130#define CLK_INFRA_GCE 10131#define CLK_INFRA_THERM 11132#define CLK_INFRA_I2C0 12133#define CLK_INFRA_I2C1 13134#define CLK_INFRA_I2C2 14135#define CLK_INFRA_I2C3 15136#define CLK_INFRA_PWM_HCLK 16137#define CLK_INFRA_PWM1 17138#define CLK_INFRA_PWM2 18139#define CLK_INFRA_PWM3 19140#define CLK_INFRA_PWM4 20141#define CLK_INFRA_PWM 21142#define CLK_INFRA_UART0 22143#define CLK_INFRA_UART1 23144#define CLK_INFRA_UART2 24145#define CLK_INFRA_UART3 25146#define CLK_INFRA_MD2MD_CCIF_0 26147#define CLK_INFRA_MD2MD_CCIF_1 27148#define CLK_INFRA_MD2MD_CCIF_2 28149#define CLK_INFRA_FHCTL 29150#define CLK_INFRA_BTIF 30151#define CLK_INFRA_MD2MD_CCIF_3 31152#define CLK_INFRA_SPI 32153#define CLK_INFRA_MSDC0 33154#define CLK_INFRA_MD2MD_CCIF_4 34155#define CLK_INFRA_MSDC1 35156#define CLK_INFRA_MSDC2 36157#define CLK_INFRA_MD2MD_CCIF_5 37158#define CLK_INFRA_GCPU 38159#define CLK_INFRA_TRNG 39160#define CLK_INFRA_AUXADC 40161#define CLK_INFRA_CPUM 41162#define CLK_INFRA_AP_C2K_CCIF_0 42163#define CLK_INFRA_AP_C2K_CCIF_1 43164#define CLK_INFRA_CLDMA 44165#define CLK_INFRA_DISP_PWM 45166#define CLK_INFRA_AP_DMA 46167#define CLK_INFRA_DEVICE_APC 47168#define CLK_INFRA_L2C_SRAM 48169#define CLK_INFRA_CCIF_AP 49170#define CLK_INFRA_AUDIO 50171#define CLK_INFRA_CCIF_MD 51172#define CLK_INFRA_DRAMC_F26M 52173#define CLK_INFRA_I2C4 53174#define CLK_INFRA_I2C_APPM 54175#define CLK_INFRA_I2C_GPUPM 55176#define CLK_INFRA_I2C2_IMM 56177#define CLK_INFRA_I2C2_ARB 57178#define CLK_INFRA_I2C3_IMM 58179#define CLK_INFRA_I2C3_ARB 59180#define CLK_INFRA_I2C5 60181#define CLK_INFRA_SYS_CIRQ 61182#define CLK_INFRA_SPI1 62183#define CLK_INFRA_DRAMC_B_F26M 63184#define CLK_INFRA_ANC_MD32 64185#define CLK_INFRA_ANC_MD32_32K 65186#define CLK_INFRA_DVFS_SPM1 66187#define CLK_INFRA_AES_TOP0 67188#define CLK_INFRA_AES_TOP1 68189#define CLK_INFRA_SSUSB_BUS 69190#define CLK_INFRA_SPI2 70191#define CLK_INFRA_SPI3 71192#define CLK_INFRA_SPI4 72193#define CLK_INFRA_SPI5 73194#define CLK_INFRA_IRTX 74195#define CLK_INFRA_SSUSB_SYS 75196#define CLK_INFRA_SSUSB_REF 76197#define CLK_INFRA_AUDIO_26M 77198#define CLK_INFRA_AUDIO_26M_PAD_TOP 78199#define CLK_INFRA_MODEM_TEMP_SHARE 79200#define CLK_INFRA_VAD_WRAP_SOC 80201#define CLK_INFRA_DRAMC_CONF 81202#define CLK_INFRA_DRAMC_B_CONF 82203#define CLK_INFRA_MFG_VCG 83204#define CLK_INFRA_13M 84205#define CLK_INFRA_NR 85206 207/* IMG_SYS */208#define CLK_IMG_FDVT 1209#define CLK_IMG_DPE 2210#define CLK_IMG_DIP 3211#define CLK_IMG_LARB6 4212#define CLK_IMG_NR 5213 214/* MM_SYS */215#define CLK_MM_SMI_COMMON 1216#define CLK_MM_SMI_LARB0 2217#define CLK_MM_SMI_LARB5 3218#define CLK_MM_CAM_MDP 4219#define CLK_MM_MDP_RDMA0 5220#define CLK_MM_MDP_RDMA1 6221#define CLK_MM_MDP_RSZ0 7222#define CLK_MM_MDP_RSZ1 8223#define CLK_MM_MDP_RSZ2 9224#define CLK_MM_MDP_TDSHP 10225#define CLK_MM_MDP_COLOR 11226#define CLK_MM_MDP_WDMA 12227#define CLK_MM_MDP_WROT0 13228#define CLK_MM_MDP_WROT1 14229#define CLK_MM_FAKE_ENG 15230#define CLK_MM_DISP_OVL0 16231#define CLK_MM_DISP_OVL1 17232#define CLK_MM_DISP_OVL0_2L 18233#define CLK_MM_DISP_OVL1_2L 19234#define CLK_MM_DISP_RDMA0 20235#define CLK_MM_DISP_RDMA1 21236#define CLK_MM_DISP_WDMA0 22237#define CLK_MM_DISP_WDMA1 23238#define CLK_MM_DISP_COLOR 24239#define CLK_MM_DISP_CCORR 25240#define CLK_MM_DISP_AAL 26241#define CLK_MM_DISP_GAMMA 27242#define CLK_MM_DISP_OD 28243#define CLK_MM_DISP_DITHER 29244#define CLK_MM_DISP_UFOE 30245#define CLK_MM_DISP_DSC 31246#define CLK_MM_DISP_SPLIT 32247#define CLK_MM_DSI0_MM_CLOCK 33248#define CLK_MM_DSI1_MM_CLOCK 34249#define CLK_MM_DPI_MM_CLOCK 35250#define CLK_MM_DPI_INTERFACE_CLOCK 36251#define CLK_MM_LARB4_AXI_ASIF_MM_CLOCK 37252#define CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK 38253#define CLK_MM_DISP_OVL0_MOUT_CLOCK 39254#define CLK_MM_FAKE_ENG2 40255#define CLK_MM_DSI0_INTERFACE_CLOCK 41256#define CLK_MM_DSI1_INTERFACE_CLOCK 42257#define CLK_MM_NR 43258 259/* VDEC_SYS */260#define CLK_VDEC_CKEN_ENG 1261#define CLK_VDEC_ACTIVE 2262#define CLK_VDEC_CKEN 3263#define CLK_VDEC_LARB1_CKEN 4264#define CLK_VDEC_NR 5265 266/* VENC_SYS */267#define CLK_VENC_0 1268#define CLK_VENC_1 2269#define CLK_VENC_2 3270#define CLK_VENC_3 4271#define CLK_VENC_NR 5272 273#endif /* _DT_BINDINGS_CLK_MT6797_H */274