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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2017 MediaTek Inc.4 * Author: Chen Zhong <chen.zhong@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_CLK_MT7622_H8#define _DT_BINDINGS_CLK_MT7622_H9 10/* TOPCKGEN */11 12#define CLK_TOP_TO_U2_PHY 013#define CLK_TOP_TO_U2_PHY_1P 114#define CLK_TOP_PCIE0_PIPE_EN 215#define CLK_TOP_PCIE1_PIPE_EN 316#define CLK_TOP_SSUSB_TX250M 417#define CLK_TOP_SSUSB_EQ_RX250M 518#define CLK_TOP_SSUSB_CDR_REF 619#define CLK_TOP_SSUSB_CDR_FB 720#define CLK_TOP_SATA_ASIC 821#define CLK_TOP_SATA_RBC 922#define CLK_TOP_TO_USB3_SYS 1023#define CLK_TOP_P1_1MHZ 1124#define CLK_TOP_4MHZ 1225#define CLK_TOP_P0_1MHZ 1326#define CLK_TOP_TXCLK_SRC_PRE 1427#define CLK_TOP_RTC 1528#define CLK_TOP_MEMPLL 1629#define CLK_TOP_DMPLL 1730#define CLK_TOP_SYSPLL_D2 1831#define CLK_TOP_SYSPLL1_D2 1932#define CLK_TOP_SYSPLL1_D4 2033#define CLK_TOP_SYSPLL1_D8 2134#define CLK_TOP_SYSPLL2_D4 2235#define CLK_TOP_SYSPLL2_D8 2336#define CLK_TOP_SYSPLL_D5 2437#define CLK_TOP_SYSPLL3_D2 2538#define CLK_TOP_SYSPLL3_D4 2639#define CLK_TOP_SYSPLL4_D2 2740#define CLK_TOP_SYSPLL4_D4 2841#define CLK_TOP_SYSPLL4_D16 2942#define CLK_TOP_UNIVPLL 3043#define CLK_TOP_UNIVPLL_D2 3144#define CLK_TOP_UNIVPLL1_D2 3245#define CLK_TOP_UNIVPLL1_D4 3346#define CLK_TOP_UNIVPLL1_D8 3447#define CLK_TOP_UNIVPLL1_D16 3548#define CLK_TOP_UNIVPLL2_D2 3649#define CLK_TOP_UNIVPLL2_D4 3750#define CLK_TOP_UNIVPLL2_D8 3851#define CLK_TOP_UNIVPLL2_D16 3952#define CLK_TOP_UNIVPLL_D5 4053#define CLK_TOP_UNIVPLL3_D2 4154#define CLK_TOP_UNIVPLL3_D4 4255#define CLK_TOP_UNIVPLL3_D16 4356#define CLK_TOP_UNIVPLL_D7 4457#define CLK_TOP_UNIVPLL_D80_D4 4558#define CLK_TOP_UNIV48M 4659#define CLK_TOP_SGMIIPLL 4760#define CLK_TOP_SGMIIPLL_D2 4861#define CLK_TOP_AUD1PLL 4962#define CLK_TOP_AUD2PLL 5063#define CLK_TOP_AUD_I2S2_MCK 5164#define CLK_TOP_TO_USB3_REF 5265#define CLK_TOP_PCIE1_MAC_EN 5366#define CLK_TOP_PCIE0_MAC_EN 5467#define CLK_TOP_ETH_500M 5568#define CLK_TOP_AXI_SEL 5669#define CLK_TOP_MEM_SEL 5770#define CLK_TOP_DDRPHYCFG_SEL 5871#define CLK_TOP_ETH_SEL 5972#define CLK_TOP_PWM_SEL 6073#define CLK_TOP_F10M_REF_SEL 6174#define CLK_TOP_NFI_INFRA_SEL 6275#define CLK_TOP_FLASH_SEL 6376#define CLK_TOP_UART_SEL 6477#define CLK_TOP_SPI0_SEL 6578#define CLK_TOP_SPI1_SEL 6679#define CLK_TOP_MSDC50_0_SEL 6780#define CLK_TOP_MSDC30_0_SEL 6881#define CLK_TOP_MSDC30_1_SEL 6982#define CLK_TOP_A1SYS_HP_SEL 7083#define CLK_TOP_A2SYS_HP_SEL 7184#define CLK_TOP_INTDIR_SEL 7285#define CLK_TOP_AUD_INTBUS_SEL 7386#define CLK_TOP_PMICSPI_SEL 7487#define CLK_TOP_SCP_SEL 7588#define CLK_TOP_ATB_SEL 7689#define CLK_TOP_HIF_SEL 7790#define CLK_TOP_AUDIO_SEL 7891#define CLK_TOP_U2_SEL 7992#define CLK_TOP_AUD1_SEL 8093#define CLK_TOP_AUD2_SEL 8194#define CLK_TOP_IRRX_SEL 8295#define CLK_TOP_IRTX_SEL 8396#define CLK_TOP_ASM_L_SEL 8497#define CLK_TOP_ASM_M_SEL 8598#define CLK_TOP_ASM_H_SEL 8699#define CLK_TOP_APLL1_SEL 87100#define CLK_TOP_APLL2_SEL 88101#define CLK_TOP_I2S0_MCK_SEL 89102#define CLK_TOP_I2S1_MCK_SEL 90103#define CLK_TOP_I2S2_MCK_SEL 91104#define CLK_TOP_I2S3_MCK_SEL 92105#define CLK_TOP_APLL1_DIV 93106#define CLK_TOP_APLL2_DIV 94107#define CLK_TOP_I2S0_MCK_DIV 95108#define CLK_TOP_I2S1_MCK_DIV 96109#define CLK_TOP_I2S2_MCK_DIV 97110#define CLK_TOP_I2S3_MCK_DIV 98111#define CLK_TOP_A1SYS_HP_DIV 99112#define CLK_TOP_A2SYS_HP_DIV 100113#define CLK_TOP_APLL1_DIV_PD 101114#define CLK_TOP_APLL2_DIV_PD 102115#define CLK_TOP_I2S0_MCK_DIV_PD 103116#define CLK_TOP_I2S1_MCK_DIV_PD 104117#define CLK_TOP_I2S2_MCK_DIV_PD 105118#define CLK_TOP_I2S3_MCK_DIV_PD 106119#define CLK_TOP_A1SYS_HP_DIV_PD 107120#define CLK_TOP_A2SYS_HP_DIV_PD 108121#define CLK_TOP_NR_CLK 109122 123/* INFRACFG */124 125#define CLK_INFRA_MUX1_SEL 0126#define CLK_INFRA_DBGCLK_PD 1127#define CLK_INFRA_AUDIO_PD 2128#define CLK_INFRA_IRRX_PD 3129#define CLK_INFRA_APXGPT_PD 4130#define CLK_INFRA_PMIC_PD 5131#define CLK_INFRA_TRNG 6132#define CLK_INFRA_NR_CLK 7133 134/* PERICFG */135 136#define CLK_PERIBUS_SEL 0137#define CLK_PERI_THERM_PD 1138#define CLK_PERI_PWM1_PD 2139#define CLK_PERI_PWM2_PD 3140#define CLK_PERI_PWM3_PD 4141#define CLK_PERI_PWM4_PD 5142#define CLK_PERI_PWM5_PD 6143#define CLK_PERI_PWM6_PD 7144#define CLK_PERI_PWM7_PD 8145#define CLK_PERI_PWM_PD 9146#define CLK_PERI_AP_DMA_PD 10147#define CLK_PERI_MSDC30_0_PD 11148#define CLK_PERI_MSDC30_1_PD 12149#define CLK_PERI_UART0_PD 13150#define CLK_PERI_UART1_PD 14151#define CLK_PERI_UART2_PD 15152#define CLK_PERI_UART3_PD 16153#define CLK_PERI_UART4_PD 17154#define CLK_PERI_BTIF_PD 18155#define CLK_PERI_I2C0_PD 19156#define CLK_PERI_I2C1_PD 20157#define CLK_PERI_I2C2_PD 21158#define CLK_PERI_SPI1_PD 22159#define CLK_PERI_AUXADC_PD 23160#define CLK_PERI_SPI0_PD 24161#define CLK_PERI_SNFI_PD 25162#define CLK_PERI_NFI_PD 26163#define CLK_PERI_NFIECC_PD 27164#define CLK_PERI_FLASH_PD 28165#define CLK_PERI_IRTX_PD 29166#define CLK_PERI_NR_CLK 30167 168/* APMIXEDSYS */169 170#define CLK_APMIXED_ARMPLL 0171#define CLK_APMIXED_MAINPLL 1172#define CLK_APMIXED_UNIV2PLL 2173#define CLK_APMIXED_ETH1PLL 3174#define CLK_APMIXED_ETH2PLL 4175#define CLK_APMIXED_AUD1PLL 5176#define CLK_APMIXED_AUD2PLL 6177#define CLK_APMIXED_TRGPLL 7178#define CLK_APMIXED_SGMIPLL 8179#define CLK_APMIXED_MAIN_CORE_EN 9180#define CLK_APMIXED_NR_CLK 10181 182/* AUDIOSYS */183 184#define CLK_AUDIO_AFE 0185#define CLK_AUDIO_HDMI 1186#define CLK_AUDIO_SPDF 2187#define CLK_AUDIO_APLL 3188#define CLK_AUDIO_I2SIN1 4189#define CLK_AUDIO_I2SIN2 5190#define CLK_AUDIO_I2SIN3 6191#define CLK_AUDIO_I2SIN4 7192#define CLK_AUDIO_I2SO1 8193#define CLK_AUDIO_I2SO2 9194#define CLK_AUDIO_I2SO3 10195#define CLK_AUDIO_I2SO4 11196#define CLK_AUDIO_ASRCI1 12197#define CLK_AUDIO_ASRCI2 13198#define CLK_AUDIO_ASRCO1 14199#define CLK_AUDIO_ASRCO2 15200#define CLK_AUDIO_INTDIR 16201#define CLK_AUDIO_A1SYS 17202#define CLK_AUDIO_A2SYS 18203#define CLK_AUDIO_UL1 19204#define CLK_AUDIO_UL2 20205#define CLK_AUDIO_UL3 21206#define CLK_AUDIO_UL4 22207#define CLK_AUDIO_UL5 23208#define CLK_AUDIO_UL6 24209#define CLK_AUDIO_DL1 25210#define CLK_AUDIO_DL2 26211#define CLK_AUDIO_DL3 27212#define CLK_AUDIO_DL4 28213#define CLK_AUDIO_DL5 29214#define CLK_AUDIO_DL6 30215#define CLK_AUDIO_DLMCH 31216#define CLK_AUDIO_ARB1 32217#define CLK_AUDIO_AWB 33218#define CLK_AUDIO_AWB2 34219#define CLK_AUDIO_DAI 35220#define CLK_AUDIO_MOD 36221#define CLK_AUDIO_ASRCI3 37222#define CLK_AUDIO_ASRCI4 38223#define CLK_AUDIO_ASRCO3 39224#define CLK_AUDIO_ASRCO4 40225#define CLK_AUDIO_MEM_ASRC1 41226#define CLK_AUDIO_MEM_ASRC2 42227#define CLK_AUDIO_MEM_ASRC3 43228#define CLK_AUDIO_MEM_ASRC4 44229#define CLK_AUDIO_MEM_ASRC5 45230#define CLK_AUDIO_AFE_CONN 46231#define CLK_AUDIO_NR_CLK 47232 233/* SSUSBSYS */234 235#define CLK_SSUSB_U2_PHY_1P_EN 0236#define CLK_SSUSB_U2_PHY_EN 1237#define CLK_SSUSB_REF_EN 2238#define CLK_SSUSB_SYS_EN 3239#define CLK_SSUSB_MCU_EN 4240#define CLK_SSUSB_DMA_EN 5241#define CLK_SSUSB_NR_CLK 6242 243/* PCIESYS */244 245#define CLK_PCIE_P1_AUX_EN 0246#define CLK_PCIE_P1_OBFF_EN 1247#define CLK_PCIE_P1_AHB_EN 2248#define CLK_PCIE_P1_AXI_EN 3249#define CLK_PCIE_P1_MAC_EN 4250#define CLK_PCIE_P1_PIPE_EN 5251#define CLK_PCIE_P0_AUX_EN 6252#define CLK_PCIE_P0_OBFF_EN 7253#define CLK_PCIE_P0_AHB_EN 8254#define CLK_PCIE_P0_AXI_EN 9255#define CLK_PCIE_P0_MAC_EN 10256#define CLK_PCIE_P0_PIPE_EN 11257#define CLK_SATA_AHB_EN 12258#define CLK_SATA_AXI_EN 13259#define CLK_SATA_ASIC_EN 14260#define CLK_SATA_RBC_EN 15261#define CLK_SATA_PM_EN 16262#define CLK_PCIE_NR_CLK 17263 264/* ETHSYS */265 266#define CLK_ETH_HSDMA_EN 0267#define CLK_ETH_ESW_EN 1268#define CLK_ETH_GP2_EN 2269#define CLK_ETH_GP1_EN 3270#define CLK_ETH_GP0_EN 4271#define CLK_ETH_NR_CLK 5272 273/* SGMIISYS */274 275#define CLK_SGMII_TX250M_EN 0276#define CLK_SGMII_RX250M_EN 1277#define CLK_SGMII_CDR_REF 2278#define CLK_SGMII_CDR_FB 3279#define CLK_SGMII_NR_CLK 4280 281#endif /* _DT_BINDINGS_CLK_MT7622_H */282 283