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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (C) 2018 MediaTek Inc.4 */5 6#ifndef _DT_BINDINGS_CLK_MT7629_H7#define _DT_BINDINGS_CLK_MT7629_H8 9/* TOPCKGEN */10#define CLK_TOP_TO_U2_PHY 011#define CLK_TOP_TO_U2_PHY_1P 112#define CLK_TOP_PCIE0_PIPE_EN 213#define CLK_TOP_PCIE1_PIPE_EN 314#define CLK_TOP_SSUSB_TX250M 415#define CLK_TOP_SSUSB_EQ_RX250M 516#define CLK_TOP_SSUSB_CDR_REF 617#define CLK_TOP_SSUSB_CDR_FB 718#define CLK_TOP_SATA_ASIC 819#define CLK_TOP_SATA_RBC 920#define CLK_TOP_TO_USB3_SYS 1021#define CLK_TOP_P1_1MHZ 1122#define CLK_TOP_4MHZ 1223#define CLK_TOP_P0_1MHZ 1324#define CLK_TOP_ETH_500M 1425#define CLK_TOP_TXCLK_SRC_PRE 1526#define CLK_TOP_RTC 1627#define CLK_TOP_PWM_QTR_26M 1728#define CLK_TOP_CPUM_TCK_IN 1829#define CLK_TOP_TO_USB3_DA_TOP 1930#define CLK_TOP_MEMPLL 2031#define CLK_TOP_DMPLL 2132#define CLK_TOP_DMPLL_D4 2233#define CLK_TOP_DMPLL_D8 2334#define CLK_TOP_SYSPLL_D2 2435#define CLK_TOP_SYSPLL1_D2 2536#define CLK_TOP_SYSPLL1_D4 2637#define CLK_TOP_SYSPLL1_D8 2738#define CLK_TOP_SYSPLL1_D16 2839#define CLK_TOP_SYSPLL2_D2 2940#define CLK_TOP_SYSPLL2_D4 3041#define CLK_TOP_SYSPLL2_D8 3142#define CLK_TOP_SYSPLL_D5 3243#define CLK_TOP_SYSPLL3_D2 3344#define CLK_TOP_SYSPLL3_D4 3445#define CLK_TOP_SYSPLL_D7 3546#define CLK_TOP_SYSPLL4_D2 3647#define CLK_TOP_SYSPLL4_D4 3748#define CLK_TOP_SYSPLL4_D16 3849#define CLK_TOP_UNIVPLL 3950#define CLK_TOP_UNIVPLL1_D2 4051#define CLK_TOP_UNIVPLL1_D4 4152#define CLK_TOP_UNIVPLL1_D8 4253#define CLK_TOP_UNIVPLL_D3 4354#define CLK_TOP_UNIVPLL2_D2 4455#define CLK_TOP_UNIVPLL2_D4 4556#define CLK_TOP_UNIVPLL2_D8 4657#define CLK_TOP_UNIVPLL2_D16 4758#define CLK_TOP_UNIVPLL_D5 4859#define CLK_TOP_UNIVPLL3_D2 4960#define CLK_TOP_UNIVPLL3_D4 5061#define CLK_TOP_UNIVPLL3_D16 5162#define CLK_TOP_UNIVPLL_D7 5263#define CLK_TOP_UNIVPLL_D80_D4 5364#define CLK_TOP_UNIV48M 5465#define CLK_TOP_SGMIIPLL_D2 5566#define CLK_TOP_CLKXTAL_D4 5667#define CLK_TOP_HD_FAXI 5768#define CLK_TOP_FAXI 5869#define CLK_TOP_F_FAUD_INTBUS 5970#define CLK_TOP_AP2WBHIF_HCLK 6071#define CLK_TOP_10M_INFRAO 6172#define CLK_TOP_MSDC30_1 6273#define CLK_TOP_SPI 6374#define CLK_TOP_SF 6475#define CLK_TOP_FLASH 6576#define CLK_TOP_TO_USB3_REF 6677#define CLK_TOP_TO_USB3_MCU 6778#define CLK_TOP_TO_USB3_DMA 6879#define CLK_TOP_FROM_TOP_AHB 6980#define CLK_TOP_FROM_TOP_AXI 7081#define CLK_TOP_PCIE1_MAC_EN 7182#define CLK_TOP_PCIE0_MAC_EN 7283#define CLK_TOP_AXI_SEL 7384#define CLK_TOP_MEM_SEL 7485#define CLK_TOP_DDRPHYCFG_SEL 7586#define CLK_TOP_ETH_SEL 7687#define CLK_TOP_PWM_SEL 7788#define CLK_TOP_F10M_REF_SEL 7889#define CLK_TOP_NFI_INFRA_SEL 7990#define CLK_TOP_FLASH_SEL 8091#define CLK_TOP_UART_SEL 8192#define CLK_TOP_SPI0_SEL 8293#define CLK_TOP_SPI1_SEL 8394#define CLK_TOP_MSDC50_0_SEL 8495#define CLK_TOP_MSDC30_0_SEL 8596#define CLK_TOP_MSDC30_1_SEL 8697#define CLK_TOP_AP2WBMCU_SEL 8798#define CLK_TOP_AP2WBHIF_SEL 8899#define CLK_TOP_AUDIO_SEL 89100#define CLK_TOP_AUD_INTBUS_SEL 90101#define CLK_TOP_PMICSPI_SEL 91102#define CLK_TOP_SCP_SEL 92103#define CLK_TOP_ATB_SEL 93104#define CLK_TOP_HIF_SEL 94105#define CLK_TOP_SATA_SEL 95106#define CLK_TOP_U2_SEL 96107#define CLK_TOP_AUD1_SEL 97108#define CLK_TOP_AUD2_SEL 98109#define CLK_TOP_IRRX_SEL 99110#define CLK_TOP_IRTX_SEL 100111#define CLK_TOP_SATA_MCU_SEL 101112#define CLK_TOP_PCIE0_MCU_SEL 102113#define CLK_TOP_PCIE1_MCU_SEL 103114#define CLK_TOP_SSUSB_MCU_SEL 104115#define CLK_TOP_CRYPTO_SEL 105116#define CLK_TOP_SGMII_REF_1_SEL 106117#define CLK_TOP_10M_SEL 107118#define CLK_TOP_NR_CLK 108119 120/* INFRACFG */121#define CLK_INFRA_MUX1_SEL 0122#define CLK_INFRA_DBGCLK_PD 1123#define CLK_INFRA_TRNG_PD 2124#define CLK_INFRA_DEVAPC_PD 3125#define CLK_INFRA_APXGPT_PD 4126#define CLK_INFRA_SEJ_PD 5127#define CLK_INFRA_NR_CLK 6128 129/* PERICFG */130#define CLK_PERIBUS_SEL 0131#define CLK_PERI_PWM1_PD 1132#define CLK_PERI_PWM2_PD 2133#define CLK_PERI_PWM3_PD 3134#define CLK_PERI_PWM4_PD 4135#define CLK_PERI_PWM5_PD 5136#define CLK_PERI_PWM6_PD 6137#define CLK_PERI_PWM7_PD 7138#define CLK_PERI_PWM_PD 8139#define CLK_PERI_AP_DMA_PD 9140#define CLK_PERI_MSDC30_1_PD 10141#define CLK_PERI_UART0_PD 11142#define CLK_PERI_UART1_PD 12143#define CLK_PERI_UART2_PD 13144#define CLK_PERI_UART3_PD 14145#define CLK_PERI_BTIF_PD 15146#define CLK_PERI_I2C0_PD 16147#define CLK_PERI_SPI0_PD 17148#define CLK_PERI_SNFI_PD 18149#define CLK_PERI_NFI_PD 19150#define CLK_PERI_NFIECC_PD 20151#define CLK_PERI_FLASH_PD 21152#define CLK_PERI_NR_CLK 22153 154/* APMIXEDSYS */155#define CLK_APMIXED_ARMPLL 0156#define CLK_APMIXED_MAINPLL 1157#define CLK_APMIXED_UNIV2PLL 2158#define CLK_APMIXED_ETH1PLL 3159#define CLK_APMIXED_ETH2PLL 4160#define CLK_APMIXED_SGMIPLL 5161#define CLK_APMIXED_MAIN_CORE_EN 6162#define CLK_APMIXED_NR_CLK 7163 164/* SSUSBSYS */165#define CLK_SSUSB_U2_PHY_1P_EN 0166#define CLK_SSUSB_U2_PHY_EN 1167#define CLK_SSUSB_REF_EN 2168#define CLK_SSUSB_SYS_EN 3169#define CLK_SSUSB_MCU_EN 4170#define CLK_SSUSB_DMA_EN 5171#define CLK_SSUSB_NR_CLK 6172 173/* PCIESYS */174#define CLK_PCIE_P1_AUX_EN 0175#define CLK_PCIE_P1_OBFF_EN 1176#define CLK_PCIE_P1_AHB_EN 2177#define CLK_PCIE_P1_AXI_EN 3178#define CLK_PCIE_P1_MAC_EN 4179#define CLK_PCIE_P1_PIPE_EN 5180#define CLK_PCIE_P0_AUX_EN 6181#define CLK_PCIE_P0_OBFF_EN 7182#define CLK_PCIE_P0_AHB_EN 8183#define CLK_PCIE_P0_AXI_EN 9184#define CLK_PCIE_P0_MAC_EN 10185#define CLK_PCIE_P0_PIPE_EN 11186#define CLK_PCIE_NR_CLK 12187 188/* ETHSYS */189#define CLK_ETH_FE_EN 0190#define CLK_ETH_GP2_EN 1191#define CLK_ETH_GP1_EN 2192#define CLK_ETH_GP0_EN 3193#define CLK_ETH_ESW_EN 4194#define CLK_ETH_NR_CLK 5195 196/* SGMIISYS */197#define CLK_SGMII_TX_EN 0198#define CLK_SGMII_RX_EN 1199#define CLK_SGMII_CDR_REF 2200#define CLK_SGMII_CDR_FB 3201#define CLK_SGMII_NR_CLK 4202 203#endif /* _DT_BINDINGS_CLK_MT7629_H */204