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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (c) 2021 MediaTek Inc.4 * Author: Sam Shih <sam.shih@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_CLK_MT7986_H8#define _DT_BINDINGS_CLK_MT7986_H9 10/* APMIXEDSYS */11 12#define CLK_APMIXED_ARMPLL 013#define CLK_APMIXED_NET2PLL 114#define CLK_APMIXED_MMPLL 215#define CLK_APMIXED_SGMPLL 316#define CLK_APMIXED_WEDMCUPLL 417#define CLK_APMIXED_NET1PLL 518#define CLK_APMIXED_MPLL 619#define CLK_APMIXED_APLL2 720 21/* TOPCKGEN */22 23#define CLK_TOP_XTAL 024#define CLK_TOP_XTAL_D2 125#define CLK_TOP_RTC_32K 226#define CLK_TOP_RTC_32P7K 327#define CLK_TOP_MPLL_D2 428#define CLK_TOP_MPLL_D4 529#define CLK_TOP_MPLL_D8 630#define CLK_TOP_MPLL_D8_D2 731#define CLK_TOP_MPLL_D3_D2 832#define CLK_TOP_MMPLL_D2 933#define CLK_TOP_MMPLL_D4 1034#define CLK_TOP_MMPLL_D8 1135#define CLK_TOP_MMPLL_D8_D2 1236#define CLK_TOP_MMPLL_D3_D8 1337#define CLK_TOP_MMPLL_U2PHY 1438#define CLK_TOP_APLL2_D4 1539#define CLK_TOP_NET1PLL_D4 1640#define CLK_TOP_NET1PLL_D5 1741#define CLK_TOP_NET1PLL_D5_D2 1842#define CLK_TOP_NET1PLL_D5_D4 1943#define CLK_TOP_NET1PLL_D8_D2 2044#define CLK_TOP_NET1PLL_D8_D4 2145#define CLK_TOP_NET2PLL_D4 2246#define CLK_TOP_NET2PLL_D4_D2 2347#define CLK_TOP_NET2PLL_D3_D2 2448#define CLK_TOP_WEDMCUPLL_D5_D2 2549#define CLK_TOP_NFI1X_SEL 2650#define CLK_TOP_SPINFI_SEL 2751#define CLK_TOP_SPI_SEL 2852#define CLK_TOP_SPIM_MST_SEL 2953#define CLK_TOP_UART_SEL 3054#define CLK_TOP_PWM_SEL 3155#define CLK_TOP_I2C_SEL 3256#define CLK_TOP_PEXTP_TL_SEL 3357#define CLK_TOP_EMMC_250M_SEL 3458#define CLK_TOP_EMMC_416M_SEL 3559#define CLK_TOP_F_26M_ADC_SEL 3660#define CLK_TOP_DRAMC_SEL 3761#define CLK_TOP_DRAMC_MD32_SEL 3862#define CLK_TOP_SYSAXI_SEL 3963#define CLK_TOP_SYSAPB_SEL 4064#define CLK_TOP_ARM_DB_MAIN_SEL 4165#define CLK_TOP_ARM_DB_JTSEL 4266#define CLK_TOP_NETSYS_SEL 4367#define CLK_TOP_NETSYS_500M_SEL 4468#define CLK_TOP_NETSYS_MCU_SEL 4569#define CLK_TOP_NETSYS_2X_SEL 4670#define CLK_TOP_SGM_325M_SEL 4771#define CLK_TOP_SGM_REG_SEL 4872#define CLK_TOP_A1SYS_SEL 4973#define CLK_TOP_CONN_MCUSYS_SEL 5074#define CLK_TOP_EIP_B_SEL 5175#define CLK_TOP_PCIE_PHY_SEL 5276#define CLK_TOP_USB3_PHY_SEL 5377#define CLK_TOP_F26M_SEL 5478#define CLK_TOP_AUD_L_SEL 5579#define CLK_TOP_A_TUNER_SEL 5680#define CLK_TOP_U2U3_SEL 5781#define CLK_TOP_U2U3_SYS_SEL 5882#define CLK_TOP_U2U3_XHCI_SEL 5983#define CLK_TOP_DA_U2_REFSEL 6084#define CLK_TOP_DA_U2_CK_1P_SEL 6185#define CLK_TOP_AP2CNN_HOST_SEL 6286#define CLK_TOP_JTAG 6387 88/* INFRACFG */89 90#define CLK_INFRA_SYSAXI_D2 091#define CLK_INFRA_UART0_SEL 192#define CLK_INFRA_UART1_SEL 293#define CLK_INFRA_UART2_SEL 394#define CLK_INFRA_SPI0_SEL 495#define CLK_INFRA_SPI1_SEL 596#define CLK_INFRA_PWM1_SEL 697#define CLK_INFRA_PWM2_SEL 798#define CLK_INFRA_PWM_BSEL 899#define CLK_INFRA_PCIE_SEL 9100#define CLK_INFRA_GPT_STA 10101#define CLK_INFRA_PWM_HCK 11102#define CLK_INFRA_PWM_STA 12103#define CLK_INFRA_PWM1_CK 13104#define CLK_INFRA_PWM2_CK 14105#define CLK_INFRA_CQ_DMA_CK 15106#define CLK_INFRA_EIP97_CK 16107#define CLK_INFRA_AUD_BUS_CK 17108#define CLK_INFRA_AUD_26M_CK 18109#define CLK_INFRA_AUD_L_CK 19110#define CLK_INFRA_AUD_AUD_CK 20111#define CLK_INFRA_AUD_EG2_CK 21112#define CLK_INFRA_DRAMC_26M_CK 22113#define CLK_INFRA_DBG_CK 23114#define CLK_INFRA_AP_DMA_CK 24115#define CLK_INFRA_SEJ_CK 25116#define CLK_INFRA_SEJ_13M_CK 26117#define CLK_INFRA_THERM_CK 27118#define CLK_INFRA_I2C0_CK 28119#define CLK_INFRA_UART0_CK 29120#define CLK_INFRA_UART1_CK 30121#define CLK_INFRA_UART2_CK 31122#define CLK_INFRA_NFI1_CK 32123#define CLK_INFRA_SPINFI1_CK 33124#define CLK_INFRA_NFI_HCK_CK 34125#define CLK_INFRA_SPI0_CK 35126#define CLK_INFRA_SPI1_CK 36127#define CLK_INFRA_SPI0_HCK_CK 37128#define CLK_INFRA_SPI1_HCK_CK 38129#define CLK_INFRA_FRTC_CK 39130#define CLK_INFRA_MSDC_CK 40131#define CLK_INFRA_MSDC_HCK_CK 41132#define CLK_INFRA_MSDC_133M_CK 42133#define CLK_INFRA_MSDC_66M_CK 43134#define CLK_INFRA_ADC_26M_CK 44135#define CLK_INFRA_ADC_FRC_CK 45136#define CLK_INFRA_FBIST2FPC_CK 46137#define CLK_INFRA_IUSB_133_CK 47138#define CLK_INFRA_IUSB_66M_CK 48139#define CLK_INFRA_IUSB_SYS_CK 49140#define CLK_INFRA_IUSB_CK 50141#define CLK_INFRA_IPCIE_CK 51142#define CLK_INFRA_IPCIE_PIPE_CK 52143#define CLK_INFRA_IPCIER_CK 53144#define CLK_INFRA_IPCIEB_CK 54145#define CLK_INFRA_TRNG_CK 55146 147/* SGMIISYS_0 */148 149#define CLK_SGMII0_TX250M_EN 0150#define CLK_SGMII0_RX250M_EN 1151#define CLK_SGMII0_CDR_REF 2152#define CLK_SGMII0_CDR_FB 3153 154/* SGMIISYS_1 */155 156#define CLK_SGMII1_TX250M_EN 0157#define CLK_SGMII1_RX250M_EN 1158#define CLK_SGMII1_CDR_REF 2159#define CLK_SGMII1_CDR_FB 3160 161/* ETHSYS */162 163#define CLK_ETH_FE_EN 0164#define CLK_ETH_GP2_EN 1165#define CLK_ETH_GP1_EN 2166#define CLK_ETH_WOCPU1_EN 3167#define CLK_ETH_WOCPU0_EN 4168 169#endif /* _DT_BINDINGS_CLK_MT7986_H */170