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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2014 MediaTek Inc.4 * Author: James Liao <jamesjj.liao@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_CLK_MT8135_H8#define _DT_BINDINGS_CLK_MT8135_H9 10/* TOPCKGEN */11 12#define CLK_TOP_DSI0_LNTC_DSICLK 113#define CLK_TOP_HDMITX_CLKDIG_CTS 214#define CLK_TOP_CLKPH_MCK 315#define CLK_TOP_CPUM_TCK_IN 416#define CLK_TOP_MAINPLL_806M 517#define CLK_TOP_MAINPLL_537P3M 618#define CLK_TOP_MAINPLL_322P4M 719#define CLK_TOP_MAINPLL_230P3M 820#define CLK_TOP_UNIVPLL_624M 921#define CLK_TOP_UNIVPLL_416M 1022#define CLK_TOP_UNIVPLL_249P6M 1123#define CLK_TOP_UNIVPLL_178P3M 1224#define CLK_TOP_UNIVPLL_48M 1325#define CLK_TOP_MMPLL_D2 1426#define CLK_TOP_MMPLL_D3 1527#define CLK_TOP_MMPLL_D5 1628#define CLK_TOP_MMPLL_D7 1729#define CLK_TOP_MMPLL_D4 1830#define CLK_TOP_MMPLL_D6 1931#define CLK_TOP_SYSPLL_D2 2032#define CLK_TOP_SYSPLL_D4 2133#define CLK_TOP_SYSPLL_D6 2234#define CLK_TOP_SYSPLL_D8 2335#define CLK_TOP_SYSPLL_D10 2436#define CLK_TOP_SYSPLL_D12 2537#define CLK_TOP_SYSPLL_D16 2638#define CLK_TOP_SYSPLL_D24 2739#define CLK_TOP_SYSPLL_D3 2840#define CLK_TOP_SYSPLL_D2P5 2941#define CLK_TOP_SYSPLL_D5 3042#define CLK_TOP_SYSPLL_D3P5 3143#define CLK_TOP_UNIVPLL1_D2 3244#define CLK_TOP_UNIVPLL1_D4 3345#define CLK_TOP_UNIVPLL1_D6 3446#define CLK_TOP_UNIVPLL1_D8 3547#define CLK_TOP_UNIVPLL1_D10 3648#define CLK_TOP_UNIVPLL2_D2 3749#define CLK_TOP_UNIVPLL2_D4 3850#define CLK_TOP_UNIVPLL2_D6 3951#define CLK_TOP_UNIVPLL2_D8 4052#define CLK_TOP_UNIVPLL_D3 4153#define CLK_TOP_UNIVPLL_D5 4254#define CLK_TOP_UNIVPLL_D7 4355#define CLK_TOP_UNIVPLL_D10 4456#define CLK_TOP_UNIVPLL_D26 4557#define CLK_TOP_APLL 4658#define CLK_TOP_APLL_D4 4759#define CLK_TOP_APLL_D8 4860#define CLK_TOP_APLL_D16 4961#define CLK_TOP_APLL_D24 5062#define CLK_TOP_LVDSPLL_D2 5163#define CLK_TOP_LVDSPLL_D4 5264#define CLK_TOP_LVDSPLL_D8 5365#define CLK_TOP_LVDSTX_CLKDIG_CT 5466#define CLK_TOP_VPLL_DPIX 5567#define CLK_TOP_TVHDMI_H 5668#define CLK_TOP_HDMITX_CLKDIG_D2 5769#define CLK_TOP_HDMITX_CLKDIG_D3 5870#define CLK_TOP_TVHDMI_D2 5971#define CLK_TOP_TVHDMI_D4 6072#define CLK_TOP_MEMPLL_MCK_D4 6173#define CLK_TOP_AXI_SEL 6274#define CLK_TOP_SMI_SEL 6375#define CLK_TOP_MFG_SEL 6476#define CLK_TOP_IRDA_SEL 6577#define CLK_TOP_CAM_SEL 6678#define CLK_TOP_AUD_INTBUS_SEL 6779#define CLK_TOP_JPG_SEL 6880#define CLK_TOP_DISP_SEL 6981#define CLK_TOP_MSDC30_1_SEL 7082#define CLK_TOP_MSDC30_2_SEL 7183#define CLK_TOP_MSDC30_3_SEL 7284#define CLK_TOP_MSDC30_4_SEL 7385#define CLK_TOP_USB20_SEL 7486#define CLK_TOP_VENC_SEL 7587#define CLK_TOP_SPI_SEL 7688#define CLK_TOP_UART_SEL 7789#define CLK_TOP_MEM_SEL 7890#define CLK_TOP_CAMTG_SEL 7991#define CLK_TOP_AUDIO_SEL 8092#define CLK_TOP_FIX_SEL 8193#define CLK_TOP_VDEC_SEL 8294#define CLK_TOP_DDRPHYCFG_SEL 8395#define CLK_TOP_DPILVDS_SEL 8496#define CLK_TOP_PMICSPI_SEL 8597#define CLK_TOP_MSDC30_0_SEL 8698#define CLK_TOP_SMI_MFG_AS_SEL 8799#define CLK_TOP_GCPU_SEL 88100#define CLK_TOP_DPI1_SEL 89101#define CLK_TOP_CCI_SEL 90102#define CLK_TOP_APLL_SEL 91103#define CLK_TOP_HDMIPLL_SEL 92104#define CLK_TOP_NR_CLK 93105 106/* APMIXED_SYS */107 108#define CLK_APMIXED_ARMPLL1 1109#define CLK_APMIXED_ARMPLL2 2110#define CLK_APMIXED_MAINPLL 3111#define CLK_APMIXED_UNIVPLL 4112#define CLK_APMIXED_MMPLL 5113#define CLK_APMIXED_MSDCPLL 6114#define CLK_APMIXED_TVDPLL 7115#define CLK_APMIXED_LVDSPLL 8116#define CLK_APMIXED_AUDPLL 9117#define CLK_APMIXED_VDECPLL 10118#define CLK_APMIXED_NR_CLK 11119 120/* INFRA_SYS */121 122#define CLK_INFRA_PMIC_WRAP 1123#define CLK_INFRA_PMICSPI 2124#define CLK_INFRA_CCIF1_AP_CTRL 3125#define CLK_INFRA_CCIF0_AP_CTRL 4126#define CLK_INFRA_KP 5127#define CLK_INFRA_CPUM 6128#define CLK_INFRA_M4U 7129#define CLK_INFRA_MFGAXI 8130#define CLK_INFRA_DEVAPC 9131#define CLK_INFRA_AUDIO 10132#define CLK_INFRA_MFG_BUS 11133#define CLK_INFRA_SMI 12134#define CLK_INFRA_DBGCLK 13135#define CLK_INFRA_NR_CLK 14136 137/* PERI_SYS */138 139#define CLK_PERI_I2C5 1140#define CLK_PERI_I2C4 2141#define CLK_PERI_I2C3 3142#define CLK_PERI_I2C2 4143#define CLK_PERI_I2C1 5144#define CLK_PERI_I2C0 6145#define CLK_PERI_UART3 7146#define CLK_PERI_UART2 8147#define CLK_PERI_UART1 9148#define CLK_PERI_UART0 10149#define CLK_PERI_IRDA 11150#define CLK_PERI_NLI 12151#define CLK_PERI_MD_HIF 13152#define CLK_PERI_AP_HIF 14153#define CLK_PERI_MSDC30_3 15154#define CLK_PERI_MSDC30_2 16155#define CLK_PERI_MSDC30_1 17156#define CLK_PERI_MSDC20_2 18157#define CLK_PERI_MSDC20_1 19158#define CLK_PERI_AP_DMA 20159#define CLK_PERI_USB1 21160#define CLK_PERI_USB0 22161#define CLK_PERI_PWM 23162#define CLK_PERI_PWM7 24163#define CLK_PERI_PWM6 25164#define CLK_PERI_PWM5 26165#define CLK_PERI_PWM4 27166#define CLK_PERI_PWM3 28167#define CLK_PERI_PWM2 29168#define CLK_PERI_PWM1 30169#define CLK_PERI_THERM 31170#define CLK_PERI_NFI 32171#define CLK_PERI_USBSLV 33172#define CLK_PERI_USB1_MCU 34173#define CLK_PERI_USB0_MCU 35174#define CLK_PERI_GCPU 36175#define CLK_PERI_FHCTL 37176#define CLK_PERI_SPI1 38177#define CLK_PERI_AUXADC 39178#define CLK_PERI_PERI_PWRAP 40179#define CLK_PERI_I2C6 41180#define CLK_PERI_UART0_SEL 42181#define CLK_PERI_UART1_SEL 43182#define CLK_PERI_UART2_SEL 44183#define CLK_PERI_UART3_SEL 45184#define CLK_PERI_NR_CLK 46185 186#endif /* _DT_BINDINGS_CLK_MT8135_H */187