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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2014 MediaTek Inc.4 * Author: James Liao <jamesjj.liao@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_CLK_MT8173_H8#define _DT_BINDINGS_CLK_MT8173_H9 10/* TOPCKGEN */11 12#define CLK_TOP_CLKPH_MCK_O 113#define CLK_TOP_USB_SYSPLL_125M 314#define CLK_TOP_HDMITX_DIG_CTS 415#define CLK_TOP_ARMCA7PLL_754M 516#define CLK_TOP_ARMCA7PLL_502M 617#define CLK_TOP_MAIN_H546M 718#define CLK_TOP_MAIN_H364M 819#define CLK_TOP_MAIN_H218P4M 920#define CLK_TOP_MAIN_H156M 1021#define CLK_TOP_TVDPLL_445P5M 1122#define CLK_TOP_TVDPLL_594M 1223#define CLK_TOP_UNIV_624M 1324#define CLK_TOP_UNIV_416M 1425#define CLK_TOP_UNIV_249P6M 1526#define CLK_TOP_UNIV_178P3M 1627#define CLK_TOP_UNIV_48M 1728#define CLK_TOP_CLKRTC_EXT 1829#define CLK_TOP_CLKRTC_INT 1930#define CLK_TOP_FPC 2031#define CLK_TOP_HDMITXPLL_D2 2132#define CLK_TOP_HDMITXPLL_D3 2233#define CLK_TOP_ARMCA7PLL_D2 2334#define CLK_TOP_ARMCA7PLL_D3 2435#define CLK_TOP_APLL1 2536#define CLK_TOP_APLL2 2637#define CLK_TOP_DMPLL 2738#define CLK_TOP_DMPLL_D2 2839#define CLK_TOP_DMPLL_D4 2940#define CLK_TOP_DMPLL_D8 3041#define CLK_TOP_DMPLL_D16 3142#define CLK_TOP_LVDSPLL_D2 3243#define CLK_TOP_LVDSPLL_D4 3344#define CLK_TOP_LVDSPLL_D8 3445#define CLK_TOP_MMPLL 3546#define CLK_TOP_MMPLL_D2 3647#define CLK_TOP_MSDCPLL 3748#define CLK_TOP_MSDCPLL_D2 3849#define CLK_TOP_MSDCPLL_D4 3950#define CLK_TOP_MSDCPLL2 4051#define CLK_TOP_MSDCPLL2_D2 4152#define CLK_TOP_MSDCPLL2_D4 4253#define CLK_TOP_SYSPLL_D2 4354#define CLK_TOP_SYSPLL1_D2 4455#define CLK_TOP_SYSPLL1_D4 4556#define CLK_TOP_SYSPLL1_D8 4657#define CLK_TOP_SYSPLL1_D16 4758#define CLK_TOP_SYSPLL_D3 4859#define CLK_TOP_SYSPLL2_D2 4960#define CLK_TOP_SYSPLL2_D4 5061#define CLK_TOP_SYSPLL_D5 5162#define CLK_TOP_SYSPLL3_D2 5263#define CLK_TOP_SYSPLL3_D4 5364#define CLK_TOP_SYSPLL_D7 5465#define CLK_TOP_SYSPLL4_D2 5566#define CLK_TOP_SYSPLL4_D4 5667#define CLK_TOP_TVDPLL 5768#define CLK_TOP_TVDPLL_D2 5869#define CLK_TOP_TVDPLL_D4 5970#define CLK_TOP_TVDPLL_D8 6071#define CLK_TOP_TVDPLL_D16 6172#define CLK_TOP_UNIVPLL_D2 6273#define CLK_TOP_UNIVPLL1_D2 6374#define CLK_TOP_UNIVPLL1_D4 6475#define CLK_TOP_UNIVPLL1_D8 6576#define CLK_TOP_UNIVPLL_D3 6677#define CLK_TOP_UNIVPLL2_D2 6778#define CLK_TOP_UNIVPLL2_D4 6879#define CLK_TOP_UNIVPLL2_D8 6980#define CLK_TOP_UNIVPLL_D5 7081#define CLK_TOP_UNIVPLL3_D2 7182#define CLK_TOP_UNIVPLL3_D4 7283#define CLK_TOP_UNIVPLL3_D8 7384#define CLK_TOP_UNIVPLL_D7 7485#define CLK_TOP_UNIVPLL_D26 7586#define CLK_TOP_UNIVPLL_D52 7687#define CLK_TOP_VCODECPLL 7788#define CLK_TOP_VCODECPLL_370P5 7889#define CLK_TOP_VENCPLL 7990#define CLK_TOP_VENCPLL_D2 8091#define CLK_TOP_VENCPLL_D4 8192#define CLK_TOP_AXI_SEL 8293#define CLK_TOP_MEM_SEL 8394#define CLK_TOP_DDRPHYCFG_SEL 8495#define CLK_TOP_MM_SEL 8596#define CLK_TOP_PWM_SEL 8697#define CLK_TOP_VDEC_SEL 8798#define CLK_TOP_VENC_SEL 8899#define CLK_TOP_MFG_SEL 89100#define CLK_TOP_CAMTG_SEL 90101#define CLK_TOP_UART_SEL 91102#define CLK_TOP_SPI_SEL 92103#define CLK_TOP_USB20_SEL 93104#define CLK_TOP_USB30_SEL 94105#define CLK_TOP_MSDC50_0_H_SEL 95106#define CLK_TOP_MSDC50_0_SEL 96107#define CLK_TOP_MSDC30_1_SEL 97108#define CLK_TOP_MSDC30_2_SEL 98109#define CLK_TOP_MSDC30_3_SEL 99110#define CLK_TOP_AUDIO_SEL 100111#define CLK_TOP_AUD_INTBUS_SEL 101112#define CLK_TOP_PMICSPI_SEL 102113#define CLK_TOP_SCP_SEL 103114#define CLK_TOP_ATB_SEL 104115#define CLK_TOP_VENC_LT_SEL 105116#define CLK_TOP_DPI0_SEL 106117#define CLK_TOP_IRDA_SEL 107118#define CLK_TOP_CCI400_SEL 108119#define CLK_TOP_AUD_1_SEL 109120#define CLK_TOP_AUD_2_SEL 110121#define CLK_TOP_MEM_MFG_IN_SEL 111122#define CLK_TOP_AXI_MFG_IN_SEL 112123#define CLK_TOP_SCAM_SEL 113124#define CLK_TOP_SPINFI_IFR_SEL 114125#define CLK_TOP_HDMI_SEL 115126#define CLK_TOP_DPILVDS_SEL 116127#define CLK_TOP_MSDC50_2_H_SEL 117128#define CLK_TOP_HDCP_SEL 118129#define CLK_TOP_HDCP_24M_SEL 119130#define CLK_TOP_RTC_SEL 120131#define CLK_TOP_APLL1_DIV0 121132#define CLK_TOP_APLL1_DIV1 122133#define CLK_TOP_APLL1_DIV2 123134#define CLK_TOP_APLL1_DIV3 124135#define CLK_TOP_APLL1_DIV4 125136#define CLK_TOP_APLL1_DIV5 126137#define CLK_TOP_APLL2_DIV0 127138#define CLK_TOP_APLL2_DIV1 128139#define CLK_TOP_APLL2_DIV2 129140#define CLK_TOP_APLL2_DIV3 130141#define CLK_TOP_APLL2_DIV4 131142#define CLK_TOP_APLL2_DIV5 132143#define CLK_TOP_I2S0_M_SEL 133144#define CLK_TOP_I2S1_M_SEL 134145#define CLK_TOP_I2S2_M_SEL 135146#define CLK_TOP_I2S3_M_SEL 136147#define CLK_TOP_I2S3_B_SEL 137148#define CLK_TOP_DSI0_DIG 138149#define CLK_TOP_DSI1_DIG 139150#define CLK_TOP_LVDS_PXL 140151#define CLK_TOP_LVDS_CTS 141152#define CLK_TOP_NR_CLK 142153 154/* APMIXED_SYS */155 156#define CLK_APMIXED_ARMCA15PLL 1157#define CLK_APMIXED_ARMCA7PLL 2158#define CLK_APMIXED_MAINPLL 3159#define CLK_APMIXED_UNIVPLL 4160#define CLK_APMIXED_MMPLL 5161#define CLK_APMIXED_MSDCPLL 6162#define CLK_APMIXED_VENCPLL 7163#define CLK_APMIXED_TVDPLL 8164#define CLK_APMIXED_MPLL 9165#define CLK_APMIXED_VCODECPLL 10166#define CLK_APMIXED_APLL1 11167#define CLK_APMIXED_APLL2 12168#define CLK_APMIXED_LVDSPLL 13169#define CLK_APMIXED_MSDCPLL2 14170#define CLK_APMIXED_REF2USB_TX 15171#define CLK_APMIXED_HDMI_REF 16172#define CLK_APMIXED_NR_CLK 17173 174/* INFRA_SYS */175 176#define CLK_INFRA_DBGCLK 1177#define CLK_INFRA_SMI 2178#define CLK_INFRA_AUDIO 3179#define CLK_INFRA_GCE 4180#define CLK_INFRA_L2C_SRAM 5181#define CLK_INFRA_M4U 6182#define CLK_INFRA_CPUM 7183#define CLK_INFRA_KP 8184#define CLK_INFRA_CEC 9185#define CLK_INFRA_PMICSPI 10186#define CLK_INFRA_PMICWRAP 11187#define CLK_INFRA_CLK_13M 12188#define CLK_INFRA_CA53SEL 13189#define CLK_INFRA_CA72SEL 14190#define CLK_INFRA_NR_CLK 15191 192/* PERI_SYS */193 194#define CLK_PERI_NFI 1195#define CLK_PERI_THERM 2196#define CLK_PERI_PWM1 3197#define CLK_PERI_PWM2 4198#define CLK_PERI_PWM3 5199#define CLK_PERI_PWM4 6200#define CLK_PERI_PWM5 7201#define CLK_PERI_PWM6 8202#define CLK_PERI_PWM7 9203#define CLK_PERI_PWM 10204#define CLK_PERI_USB0 11205#define CLK_PERI_USB1 12206#define CLK_PERI_AP_DMA 13207#define CLK_PERI_MSDC30_0 14208#define CLK_PERI_MSDC30_1 15209#define CLK_PERI_MSDC30_2 16210#define CLK_PERI_MSDC30_3 17211#define CLK_PERI_NLI_ARB 18212#define CLK_PERI_IRDA 19213#define CLK_PERI_UART0 20214#define CLK_PERI_UART1 21215#define CLK_PERI_UART2 22216#define CLK_PERI_UART3 23217#define CLK_PERI_I2C0 24218#define CLK_PERI_I2C1 25219#define CLK_PERI_I2C2 26220#define CLK_PERI_I2C3 27221#define CLK_PERI_I2C4 28222#define CLK_PERI_AUXADC 29223#define CLK_PERI_SPI0 30224#define CLK_PERI_I2C5 31225#define CLK_PERI_NFIECC 32226#define CLK_PERI_SPI 33227#define CLK_PERI_IRRX 34228#define CLK_PERI_I2C6 35229#define CLK_PERI_UART0_SEL 36230#define CLK_PERI_UART1_SEL 37231#define CLK_PERI_UART2_SEL 38232#define CLK_PERI_UART3_SEL 39233#define CLK_PERI_NR_CLK 40234 235/* IMG_SYS */236 237#define CLK_IMG_LARB2_SMI 1238#define CLK_IMG_CAM_SMI 2239#define CLK_IMG_CAM_CAM 3240#define CLK_IMG_SEN_TG 4241#define CLK_IMG_SEN_CAM 5242#define CLK_IMG_CAM_SV 6243#define CLK_IMG_FD 7244#define CLK_IMG_NR_CLK 8245 246/* MM_SYS */247 248#define CLK_MM_SMI_COMMON 1249#define CLK_MM_SMI_LARB0 2250#define CLK_MM_CAM_MDP 3251#define CLK_MM_MDP_RDMA0 4252#define CLK_MM_MDP_RDMA1 5253#define CLK_MM_MDP_RSZ0 6254#define CLK_MM_MDP_RSZ1 7255#define CLK_MM_MDP_RSZ2 8256#define CLK_MM_MDP_TDSHP0 9257#define CLK_MM_MDP_TDSHP1 10258#define CLK_MM_MDP_WDMA 11259#define CLK_MM_MDP_WROT0 12260#define CLK_MM_MDP_WROT1 13261#define CLK_MM_FAKE_ENG 14262#define CLK_MM_MUTEX_32K 15263#define CLK_MM_DISP_OVL0 16264#define CLK_MM_DISP_OVL1 17265#define CLK_MM_DISP_RDMA0 18266#define CLK_MM_DISP_RDMA1 19267#define CLK_MM_DISP_RDMA2 20268#define CLK_MM_DISP_WDMA0 21269#define CLK_MM_DISP_WDMA1 22270#define CLK_MM_DISP_COLOR0 23271#define CLK_MM_DISP_COLOR1 24272#define CLK_MM_DISP_AAL 25273#define CLK_MM_DISP_GAMMA 26274#define CLK_MM_DISP_UFOE 27275#define CLK_MM_DISP_SPLIT0 28276#define CLK_MM_DISP_SPLIT1 29277#define CLK_MM_DISP_MERGE 30278#define CLK_MM_DISP_OD 31279#define CLK_MM_DISP_PWM0MM 32280#define CLK_MM_DISP_PWM026M 33281#define CLK_MM_DISP_PWM1MM 34282#define CLK_MM_DISP_PWM126M 35283#define CLK_MM_DSI0_ENGINE 36284#define CLK_MM_DSI0_DIGITAL 37285#define CLK_MM_DSI1_ENGINE 38286#define CLK_MM_DSI1_DIGITAL 39287#define CLK_MM_DPI_PIXEL 40288#define CLK_MM_DPI_ENGINE 41289#define CLK_MM_DPI1_PIXEL 42290#define CLK_MM_DPI1_ENGINE 43291#define CLK_MM_HDMI_PIXEL 44292#define CLK_MM_HDMI_PLLCK 45293#define CLK_MM_HDMI_AUDIO 46294#define CLK_MM_HDMI_SPDIF 47295#define CLK_MM_LVDS_PIXEL 48296#define CLK_MM_LVDS_CTS 49297#define CLK_MM_SMI_LARB4 50298#define CLK_MM_HDMI_HDCP 51299#define CLK_MM_HDMI_HDCP24M 52300#define CLK_MM_NR_CLK 53301 302/* VDEC_SYS */303 304#define CLK_VDEC_CKEN 1305#define CLK_VDEC_LARB_CKEN 2306#define CLK_VDEC_NR_CLK 3307 308/* VENC_SYS */309 310#define CLK_VENC_CKE0 1311#define CLK_VENC_CKE1 2312#define CLK_VENC_CKE2 3313#define CLK_VENC_CKE3 4314#define CLK_VENC_NR_CLK 5315 316/* VENCLT_SYS */317 318#define CLK_VENCLT_CKE0 1319#define CLK_VENCLT_CKE1 2320#define CLK_VENCLT_NR_CLK 3321 322#endif /* _DT_BINDINGS_CLK_MT8173_H */323