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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2018 MediaTek Inc.4 * Author: Weiyi Lu <weiyi.lu@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_CLK_MT8183_H8#define _DT_BINDINGS_CLK_MT8183_H9 10/* APMIXED */11#define CLK_APMIXED_ARMPLL_LL 012#define CLK_APMIXED_ARMPLL_L 113#define CLK_APMIXED_CCIPLL 214#define CLK_APMIXED_MAINPLL 315#define CLK_APMIXED_UNIV2PLL 416#define CLK_APMIXED_MSDCPLL 517#define CLK_APMIXED_MMPLL 618#define CLK_APMIXED_MFGPLL 719#define CLK_APMIXED_TVDPLL 820#define CLK_APMIXED_APLL1 921#define CLK_APMIXED_APLL2 1022#define CLK_APMIXED_SSUSB_26M 1123#define CLK_APMIXED_APPLL_26M 1224#define CLK_APMIXED_MIPIC0_26M 1325#define CLK_APMIXED_MDPLLGP_26M 1426#define CLK_APMIXED_MMSYS_26M 1527#define CLK_APMIXED_UFS_26M 1628#define CLK_APMIXED_MIPIC1_26M 1729#define CLK_APMIXED_MEMPLL_26M 1830#define CLK_APMIXED_CLKSQ_LVPLL_26M 1931#define CLK_APMIXED_MIPID0_26M 2032#define CLK_APMIXED_MIPID1_26M 2133#define CLK_APMIXED_NR_CLK 2234 35/* TOPCKGEN */36#define CLK_TOP_MUX_AXI 037#define CLK_TOP_MUX_MM 138#define CLK_TOP_MUX_CAM 239#define CLK_TOP_MUX_MFG 340#define CLK_TOP_MUX_CAMTG 441#define CLK_TOP_MUX_UART 542#define CLK_TOP_MUX_SPI 643#define CLK_TOP_MUX_MSDC50_0_HCLK 744#define CLK_TOP_MUX_MSDC50_0 845#define CLK_TOP_MUX_MSDC30_1 946#define CLK_TOP_MUX_MSDC30_2 1047#define CLK_TOP_MUX_AUDIO 1148#define CLK_TOP_MUX_AUD_INTBUS 1249#define CLK_TOP_MUX_FPWRAP_ULPOSC 1350#define CLK_TOP_MUX_SCP 1451#define CLK_TOP_MUX_ATB 1552#define CLK_TOP_MUX_SSPM 1653#define CLK_TOP_MUX_DPI0 1754#define CLK_TOP_MUX_SCAM 1855#define CLK_TOP_MUX_AUD_1 1956#define CLK_TOP_MUX_AUD_2 2057#define CLK_TOP_MUX_DISP_PWM 2158#define CLK_TOP_MUX_SSUSB_TOP_XHCI 2259#define CLK_TOP_MUX_USB_TOP 2360#define CLK_TOP_MUX_SPM 2461#define CLK_TOP_MUX_I2C 2562#define CLK_TOP_MUX_F52M_MFG 2663#define CLK_TOP_MUX_SENINF 2764#define CLK_TOP_MUX_DXCC 2865#define CLK_TOP_MUX_CAMTG2 2966#define CLK_TOP_MUX_AUD_ENG1 3067#define CLK_TOP_MUX_AUD_ENG2 3168#define CLK_TOP_MUX_FAES_UFSFDE 3269#define CLK_TOP_MUX_FUFS 3370#define CLK_TOP_MUX_IMG 3471#define CLK_TOP_MUX_DSP 3572#define CLK_TOP_MUX_DSP1 3673#define CLK_TOP_MUX_DSP2 3774#define CLK_TOP_MUX_IPU_IF 3875#define CLK_TOP_MUX_CAMTG3 3976#define CLK_TOP_MUX_CAMTG4 4077#define CLK_TOP_MUX_PMICSPI 4178#define CLK_TOP_SYSPLL_CK 4279#define CLK_TOP_SYSPLL_D2 4380#define CLK_TOP_SYSPLL_D3 4481#define CLK_TOP_SYSPLL_D5 4582#define CLK_TOP_SYSPLL_D7 4683#define CLK_TOP_SYSPLL_D2_D2 4784#define CLK_TOP_SYSPLL_D2_D4 4885#define CLK_TOP_SYSPLL_D2_D8 4986#define CLK_TOP_SYSPLL_D2_D16 5087#define CLK_TOP_SYSPLL_D3_D2 5188#define CLK_TOP_SYSPLL_D3_D4 5289#define CLK_TOP_SYSPLL_D3_D8 5390#define CLK_TOP_SYSPLL_D5_D2 5491#define CLK_TOP_SYSPLL_D5_D4 5592#define CLK_TOP_SYSPLL_D7_D2 5693#define CLK_TOP_SYSPLL_D7_D4 5794#define CLK_TOP_UNIVPLL_CK 5895#define CLK_TOP_UNIVPLL_D2 5996#define CLK_TOP_UNIVPLL_D3 6097#define CLK_TOP_UNIVPLL_D5 6198#define CLK_TOP_UNIVPLL_D7 6299#define CLK_TOP_UNIVPLL_D2_D2 63100#define CLK_TOP_UNIVPLL_D2_D4 64101#define CLK_TOP_UNIVPLL_D2_D8 65102#define CLK_TOP_UNIVPLL_D3_D2 66103#define CLK_TOP_UNIVPLL_D3_D4 67104#define CLK_TOP_UNIVPLL_D3_D8 68105#define CLK_TOP_UNIVPLL_D5_D2 69106#define CLK_TOP_UNIVPLL_D5_D4 70107#define CLK_TOP_UNIVPLL_D5_D8 71108#define CLK_TOP_APLL1_CK 72109#define CLK_TOP_APLL1_D2 73110#define CLK_TOP_APLL1_D4 74111#define CLK_TOP_APLL1_D8 75112#define CLK_TOP_APLL2_CK 76113#define CLK_TOP_APLL2_D2 77114#define CLK_TOP_APLL2_D4 78115#define CLK_TOP_APLL2_D8 79116#define CLK_TOP_TVDPLL_CK 80117#define CLK_TOP_TVDPLL_D2 81118#define CLK_TOP_TVDPLL_D4 82119#define CLK_TOP_TVDPLL_D8 83120#define CLK_TOP_TVDPLL_D16 84121#define CLK_TOP_MSDCPLL_CK 85122#define CLK_TOP_MSDCPLL_D2 86123#define CLK_TOP_MSDCPLL_D4 87124#define CLK_TOP_MSDCPLL_D8 88125#define CLK_TOP_MSDCPLL_D16 89126#define CLK_TOP_AD_OSC_CK 90127#define CLK_TOP_OSC_D2 91128#define CLK_TOP_OSC_D4 92129#define CLK_TOP_OSC_D8 93130#define CLK_TOP_OSC_D16 94131#define CLK_TOP_F26M_CK_D2 95132#define CLK_TOP_MFGPLL_CK 96133#define CLK_TOP_UNIVP_192M_CK 97134#define CLK_TOP_UNIVP_192M_D2 98135#define CLK_TOP_UNIVP_192M_D4 99136#define CLK_TOP_UNIVP_192M_D8 100137#define CLK_TOP_UNIVP_192M_D16 101138#define CLK_TOP_UNIVP_192M_D32 102139#define CLK_TOP_MMPLL_CK 103140#define CLK_TOP_MMPLL_D4 104141#define CLK_TOP_MMPLL_D4_D2 105142#define CLK_TOP_MMPLL_D4_D4 106143#define CLK_TOP_MMPLL_D5 107144#define CLK_TOP_MMPLL_D5_D2 108145#define CLK_TOP_MMPLL_D5_D4 109146#define CLK_TOP_MMPLL_D6 110147#define CLK_TOP_MMPLL_D7 111148#define CLK_TOP_CLK26M 112149#define CLK_TOP_CLK13M 113150#define CLK_TOP_ULPOSC 114151#define CLK_TOP_UNIVP_192M 115152#define CLK_TOP_MUX_APLL_I2S0 116153#define CLK_TOP_MUX_APLL_I2S1 117154#define CLK_TOP_MUX_APLL_I2S2 118155#define CLK_TOP_MUX_APLL_I2S3 119156#define CLK_TOP_MUX_APLL_I2S4 120157#define CLK_TOP_MUX_APLL_I2S5 121158#define CLK_TOP_APLL12_DIV0 122159#define CLK_TOP_APLL12_DIV1 123160#define CLK_TOP_APLL12_DIV2 124161#define CLK_TOP_APLL12_DIV3 125162#define CLK_TOP_APLL12_DIV4 126163#define CLK_TOP_APLL12_DIVB 127164#define CLK_TOP_UNIVPLL 128165#define CLK_TOP_ARMPLL_DIV_PLL1 129166#define CLK_TOP_ARMPLL_DIV_PLL2 130167#define CLK_TOP_UNIVPLL_D3_D16 131168#define CLK_TOP_NR_CLK 132169 170/* CAMSYS */171#define CLK_CAM_LARB6 0172#define CLK_CAM_DFP_VAD 1173#define CLK_CAM_CAM 2174#define CLK_CAM_CAMTG 3175#define CLK_CAM_SENINF 4176#define CLK_CAM_CAMSV0 5177#define CLK_CAM_CAMSV1 6178#define CLK_CAM_CAMSV2 7179#define CLK_CAM_CCU 8180#define CLK_CAM_LARB3 9181#define CLK_CAM_NR_CLK 10182 183/* INFRACFG_AO */184#define CLK_INFRA_PMIC_TMR 0185#define CLK_INFRA_PMIC_AP 1186#define CLK_INFRA_PMIC_MD 2187#define CLK_INFRA_PMIC_CONN 3188#define CLK_INFRA_SCPSYS 4189#define CLK_INFRA_SEJ 5190#define CLK_INFRA_APXGPT 6191#define CLK_INFRA_ICUSB 7192#define CLK_INFRA_GCE 8193#define CLK_INFRA_THERM 9194#define CLK_INFRA_I2C0 10195#define CLK_INFRA_I2C1 11196#define CLK_INFRA_I2C2 12197#define CLK_INFRA_I2C3 13198#define CLK_INFRA_PWM_HCLK 14199#define CLK_INFRA_PWM1 15200#define CLK_INFRA_PWM2 16201#define CLK_INFRA_PWM3 17202#define CLK_INFRA_PWM4 18203#define CLK_INFRA_PWM 19204#define CLK_INFRA_UART0 20205#define CLK_INFRA_UART1 21206#define CLK_INFRA_UART2 22207#define CLK_INFRA_UART3 23208#define CLK_INFRA_GCE_26M 24209#define CLK_INFRA_CQ_DMA_FPC 25210#define CLK_INFRA_BTIF 26211#define CLK_INFRA_SPI0 27212#define CLK_INFRA_MSDC0 28213#define CLK_INFRA_MSDC1 29214#define CLK_INFRA_MSDC2 30215#define CLK_INFRA_MSDC0_SCK 31216#define CLK_INFRA_DVFSRC 32217#define CLK_INFRA_GCPU 33218#define CLK_INFRA_TRNG 34219#define CLK_INFRA_AUXADC 35220#define CLK_INFRA_CPUM 36221#define CLK_INFRA_CCIF1_AP 37222#define CLK_INFRA_CCIF1_MD 38223#define CLK_INFRA_AUXADC_MD 39224#define CLK_INFRA_MSDC1_SCK 40225#define CLK_INFRA_MSDC2_SCK 41226#define CLK_INFRA_AP_DMA 42227#define CLK_INFRA_XIU 43228#define CLK_INFRA_DEVICE_APC 44229#define CLK_INFRA_CCIF_AP 45230#define CLK_INFRA_DEBUGSYS 46231#define CLK_INFRA_AUDIO 47232#define CLK_INFRA_CCIF_MD 48233#define CLK_INFRA_DXCC_SEC_CORE 49234#define CLK_INFRA_DXCC_AO 50235#define CLK_INFRA_DRAMC_F26M 51236#define CLK_INFRA_IRTX 52237#define CLK_INFRA_DISP_PWM 53238#define CLK_INFRA_CLDMA_BCLK 54239#define CLK_INFRA_AUDIO_26M_BCLK 55240#define CLK_INFRA_SPI1 56241#define CLK_INFRA_I2C4 57242#define CLK_INFRA_MODEM_TEMP_SHARE 58243#define CLK_INFRA_SPI2 59244#define CLK_INFRA_SPI3 60245#define CLK_INFRA_UNIPRO_SCK 61246#define CLK_INFRA_UNIPRO_TICK 62247#define CLK_INFRA_UFS_MP_SAP_BCLK 63248#define CLK_INFRA_MD32_BCLK 64249#define CLK_INFRA_SSPM 65250#define CLK_INFRA_UNIPRO_MBIST 66251#define CLK_INFRA_SSPM_BUS_HCLK 67252#define CLK_INFRA_I2C5 68253#define CLK_INFRA_I2C5_ARBITER 69254#define CLK_INFRA_I2C5_IMM 70255#define CLK_INFRA_I2C1_ARBITER 71256#define CLK_INFRA_I2C1_IMM 72257#define CLK_INFRA_I2C2_ARBITER 73258#define CLK_INFRA_I2C2_IMM 74259#define CLK_INFRA_SPI4 75260#define CLK_INFRA_SPI5 76261#define CLK_INFRA_CQ_DMA 77262#define CLK_INFRA_UFS 78263#define CLK_INFRA_AES_UFSFDE 79264#define CLK_INFRA_UFS_TICK 80265#define CLK_INFRA_MSDC0_SELF 81266#define CLK_INFRA_MSDC1_SELF 82267#define CLK_INFRA_MSDC2_SELF 83268#define CLK_INFRA_SSPM_26M_SELF 84269#define CLK_INFRA_SSPM_32K_SELF 85270#define CLK_INFRA_UFS_AXI 86271#define CLK_INFRA_I2C6 87272#define CLK_INFRA_AP_MSDC0 88273#define CLK_INFRA_MD_MSDC0 89274#define CLK_INFRA_USB 90275#define CLK_INFRA_DEVMPU_BCLK 91276#define CLK_INFRA_CCIF2_AP 92277#define CLK_INFRA_CCIF2_MD 93278#define CLK_INFRA_CCIF3_AP 94279#define CLK_INFRA_CCIF3_MD 95280#define CLK_INFRA_SEJ_F13M 96281#define CLK_INFRA_AES_BCLK 97282#define CLK_INFRA_I2C7 98283#define CLK_INFRA_I2C8 99284#define CLK_INFRA_FBIST2FPC 100285#define CLK_INFRA_NR_CLK 101286 287/* PERICFG */288#define CLK_PERI_AXI 0289#define CLK_PERI_NR_CLK 1290 291/* MFGCFG */292#define CLK_MFG_BG3D 0293#define CLK_MFG_NR_CLK 1294 295/* IMG */296#define CLK_IMG_OWE 0297#define CLK_IMG_WPE_B 1298#define CLK_IMG_WPE_A 2299#define CLK_IMG_MFB 3300#define CLK_IMG_RSC 4301#define CLK_IMG_DPE 5302#define CLK_IMG_FDVT 6303#define CLK_IMG_DIP 7304#define CLK_IMG_LARB2 8305#define CLK_IMG_LARB5 9306#define CLK_IMG_NR_CLK 10307 308/* MMSYS_CONFIG */309#define CLK_MM_SMI_COMMON 0310#define CLK_MM_SMI_LARB0 1311#define CLK_MM_SMI_LARB1 2312#define CLK_MM_GALS_COMM0 3313#define CLK_MM_GALS_COMM1 4314#define CLK_MM_GALS_CCU2MM 5315#define CLK_MM_GALS_IPU12MM 6316#define CLK_MM_GALS_IMG2MM 7317#define CLK_MM_GALS_CAM2MM 8318#define CLK_MM_GALS_IPU2MM 9319#define CLK_MM_MDP_DL_TXCK 10320#define CLK_MM_IPU_DL_TXCK 11321#define CLK_MM_MDP_RDMA0 12322#define CLK_MM_MDP_RDMA1 13323#define CLK_MM_MDP_RSZ0 14324#define CLK_MM_MDP_RSZ1 15325#define CLK_MM_MDP_TDSHP 16326#define CLK_MM_MDP_WROT0 17327#define CLK_MM_FAKE_ENG 18328#define CLK_MM_DISP_OVL0 19329#define CLK_MM_DISP_OVL0_2L 20330#define CLK_MM_DISP_OVL1_2L 21331#define CLK_MM_DISP_RDMA0 22332#define CLK_MM_DISP_RDMA1 23333#define CLK_MM_DISP_WDMA0 24334#define CLK_MM_DISP_COLOR0 25335#define CLK_MM_DISP_CCORR0 26336#define CLK_MM_DISP_AAL0 27337#define CLK_MM_DISP_GAMMA0 28338#define CLK_MM_DISP_DITHER0 29339#define CLK_MM_DISP_SPLIT 30340#define CLK_MM_DSI0_MM 31341#define CLK_MM_DSI0_IF 32342#define CLK_MM_DPI_MM 33343#define CLK_MM_DPI_IF 34344#define CLK_MM_FAKE_ENG2 35345#define CLK_MM_MDP_DL_RX 36346#define CLK_MM_IPU_DL_RX 37347#define CLK_MM_26M 38348#define CLK_MM_MMSYS_R2Y 39349#define CLK_MM_DISP_RSZ 40350#define CLK_MM_MDP_WDMA0 41351#define CLK_MM_MDP_AAL 42352#define CLK_MM_MDP_CCORR 43353#define CLK_MM_DBI_MM 44354#define CLK_MM_DBI_IF 45355#define CLK_MM_NR_CLK 46356 357/* VDEC_GCON */358#define CLK_VDEC_VDEC 0359#define CLK_VDEC_LARB1 1360#define CLK_VDEC_NR_CLK 2361 362/* VENC_GCON */363#define CLK_VENC_LARB 0364#define CLK_VENC_VENC 1365#define CLK_VENC_JPGENC 2366#define CLK_VENC_NR_CLK 3367 368/* AUDIO */369#define CLK_AUDIO_TML 0370#define CLK_AUDIO_DAC_PREDIS 1371#define CLK_AUDIO_DAC 2372#define CLK_AUDIO_ADC 3373#define CLK_AUDIO_APLL_TUNER 4374#define CLK_AUDIO_APLL2_TUNER 5375#define CLK_AUDIO_24M 6376#define CLK_AUDIO_22M 7377#define CLK_AUDIO_AFE 8378#define CLK_AUDIO_I2S4 9379#define CLK_AUDIO_I2S3 10380#define CLK_AUDIO_I2S2 11381#define CLK_AUDIO_I2S1 12382#define CLK_AUDIO_PDN_ADDA6_ADC 13383#define CLK_AUDIO_TDM 14384#define CLK_AUDIO_NR_CLK 15385 386/* IPU_CONN */387#define CLK_IPU_CONN_IPU 0388#define CLK_IPU_CONN_AHB 1389#define CLK_IPU_CONN_AXI 2390#define CLK_IPU_CONN_ISP 3391#define CLK_IPU_CONN_CAM_ADL 4392#define CLK_IPU_CONN_IMG_ADL 5393#define CLK_IPU_CONN_DAP_RX 6394#define CLK_IPU_CONN_APB2AXI 7395#define CLK_IPU_CONN_APB2AHB 8396#define CLK_IPU_CONN_IPU_CAB1TO2 9397#define CLK_IPU_CONN_IPU1_CAB1TO2 10398#define CLK_IPU_CONN_IPU2_CAB1TO2 11399#define CLK_IPU_CONN_CAB3TO3 12400#define CLK_IPU_CONN_CAB2TO1 13401#define CLK_IPU_CONN_CAB3TO1_SLICE 14402#define CLK_IPU_CONN_NR_CLK 15403 404/* IPU_ADL */405#define CLK_IPU_ADL_CABGEN 0406#define CLK_IPU_ADL_NR_CLK 1407 408/* IPU_CORE0 */409#define CLK_IPU_CORE0_JTAG 0410#define CLK_IPU_CORE0_AXI 1411#define CLK_IPU_CORE0_IPU 2412#define CLK_IPU_CORE0_NR_CLK 3413 414/* IPU_CORE1 */415#define CLK_IPU_CORE1_JTAG 0416#define CLK_IPU_CORE1_AXI 1417#define CLK_IPU_CORE1_IPU 2418#define CLK_IPU_CORE1_NR_CLK 3419 420/* MCUCFG */421#define CLK_MCU_MP0_SEL 0422#define CLK_MCU_MP2_SEL 1423#define CLK_MCU_BUS_SEL 2424#define CLK_MCU_NR_CLK 3425 426#endif /* _DT_BINDINGS_CLK_MT8183_H */427