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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */2/*3 * Copyright (c) 2022 MediaTek Inc.4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_CLK_MT8186_H8#define _DT_BINDINGS_CLK_MT8186_H9 10/* MCUSYS */11 12#define CLK_MCU_ARMPLL_LL_SEL 013#define CLK_MCU_ARMPLL_BL_SEL 114#define CLK_MCU_ARMPLL_BUS_SEL 215#define CLK_MCU_NR_CLK 316 17/* TOPCKGEN */18 19#define CLK_TOP_AXI 020#define CLK_TOP_SCP 121#define CLK_TOP_MFG 222#define CLK_TOP_CAMTG 323#define CLK_TOP_CAMTG1 424#define CLK_TOP_CAMTG2 525#define CLK_TOP_CAMTG3 626#define CLK_TOP_CAMTG4 727#define CLK_TOP_CAMTG5 828#define CLK_TOP_CAMTG6 929#define CLK_TOP_UART 1030#define CLK_TOP_SPI 1131#define CLK_TOP_MSDC50_0_HCLK 1232#define CLK_TOP_MSDC50_0 1333#define CLK_TOP_MSDC30_1 1434#define CLK_TOP_AUDIO 1535#define CLK_TOP_AUD_INTBUS 1636#define CLK_TOP_AUD_1 1737#define CLK_TOP_AUD_2 1838#define CLK_TOP_AUD_ENGEN1 1939#define CLK_TOP_AUD_ENGEN2 2040#define CLK_TOP_DISP_PWM 2141#define CLK_TOP_SSPM 2242#define CLK_TOP_DXCC 2343#define CLK_TOP_USB_TOP 2444#define CLK_TOP_SRCK 2545#define CLK_TOP_SPM 2646#define CLK_TOP_I2C 2747#define CLK_TOP_PWM 2848#define CLK_TOP_SENINF 2949#define CLK_TOP_SENINF1 3050#define CLK_TOP_SENINF2 3151#define CLK_TOP_SENINF3 3252#define CLK_TOP_AES_MSDCFDE 3353#define CLK_TOP_PWRAP_ULPOSC 3454#define CLK_TOP_CAMTM 3555#define CLK_TOP_VENC 3656#define CLK_TOP_CAM 3757#define CLK_TOP_IMG1 3858#define CLK_TOP_IPE 3959#define CLK_TOP_DPMAIF 4060#define CLK_TOP_VDEC 4161#define CLK_TOP_DISP 4262#define CLK_TOP_MDP 4363#define CLK_TOP_AUDIO_H 4464#define CLK_TOP_UFS 4565#define CLK_TOP_AES_FDE 4666#define CLK_TOP_AUDIODSP 4767#define CLK_TOP_DVFSRC 4868#define CLK_TOP_DSI_OCC 4969#define CLK_TOP_SPMI_MST 5070#define CLK_TOP_SPINOR 5171#define CLK_TOP_NNA 5272#define CLK_TOP_NNA1 5373#define CLK_TOP_NNA2 5474#define CLK_TOP_SSUSB_XHCI 5575#define CLK_TOP_SSUSB_TOP_1P 5676#define CLK_TOP_SSUSB_XHCI_1P 5777#define CLK_TOP_WPE 5878#define CLK_TOP_DPI 5979#define CLK_TOP_U3_OCC_250M 6080#define CLK_TOP_U3_OCC_500M 6181#define CLK_TOP_ADSP_BUS 6282#define CLK_TOP_APLL_I2S0_MCK_SEL 6383#define CLK_TOP_APLL_I2S1_MCK_SEL 6484#define CLK_TOP_APLL_I2S2_MCK_SEL 6585#define CLK_TOP_APLL_I2S4_MCK_SEL 6686#define CLK_TOP_APLL_TDMOUT_MCK_SEL 6787#define CLK_TOP_MAINPLL_D2 6888#define CLK_TOP_MAINPLL_D2_D2 6989#define CLK_TOP_MAINPLL_D2_D4 7090#define CLK_TOP_MAINPLL_D2_D16 7191#define CLK_TOP_MAINPLL_D3 7292#define CLK_TOP_MAINPLL_D3_D2 7393#define CLK_TOP_MAINPLL_D3_D4 7494#define CLK_TOP_MAINPLL_D5 7595#define CLK_TOP_MAINPLL_D5_D2 7696#define CLK_TOP_MAINPLL_D5_D4 7797#define CLK_TOP_MAINPLL_D7 7898#define CLK_TOP_MAINPLL_D7_D2 7999#define CLK_TOP_MAINPLL_D7_D4 80100#define CLK_TOP_UNIVPLL 81101#define CLK_TOP_UNIVPLL_D2 82102#define CLK_TOP_UNIVPLL_D2_D2 83103#define CLK_TOP_UNIVPLL_D2_D4 84104#define CLK_TOP_UNIVPLL_D3 85105#define CLK_TOP_UNIVPLL_D3_D2 86106#define CLK_TOP_UNIVPLL_D3_D4 87107#define CLK_TOP_UNIVPLL_D3_D8 88108#define CLK_TOP_UNIVPLL_D3_D32 89109#define CLK_TOP_UNIVPLL_D5 90110#define CLK_TOP_UNIVPLL_D5_D2 91111#define CLK_TOP_UNIVPLL_D5_D4 92112#define CLK_TOP_UNIVPLL_D7 93113#define CLK_TOP_UNIVPLL_192M 94114#define CLK_TOP_UNIVPLL_192M_D4 95115#define CLK_TOP_UNIVPLL_192M_D8 96116#define CLK_TOP_UNIVPLL_192M_D16 97117#define CLK_TOP_UNIVPLL_192M_D32 98118#define CLK_TOP_APLL1_D2 99119#define CLK_TOP_APLL1_D4 100120#define CLK_TOP_APLL1_D8 101121#define CLK_TOP_APLL2_D2 102122#define CLK_TOP_APLL2_D4 103123#define CLK_TOP_APLL2_D8 104124#define CLK_TOP_MMPLL_D2 105125#define CLK_TOP_TVDPLL_D2 106126#define CLK_TOP_TVDPLL_D4 107127#define CLK_TOP_TVDPLL_D8 108128#define CLK_TOP_TVDPLL_D16 109129#define CLK_TOP_TVDPLL_D32 110130#define CLK_TOP_MSDCPLL_D2 111131#define CLK_TOP_ULPOSC1 112132#define CLK_TOP_ULPOSC1_D2 113133#define CLK_TOP_ULPOSC1_D4 114134#define CLK_TOP_ULPOSC1_D8 115135#define CLK_TOP_ULPOSC1_D10 116136#define CLK_TOP_ULPOSC1_D16 117137#define CLK_TOP_ULPOSC1_D32 118138#define CLK_TOP_ADSPPLL_D2 119139#define CLK_TOP_ADSPPLL_D4 120140#define CLK_TOP_ADSPPLL_D8 121141#define CLK_TOP_NNAPLL_D2 122142#define CLK_TOP_NNAPLL_D4 123143#define CLK_TOP_NNAPLL_D8 124144#define CLK_TOP_NNA2PLL_D2 125145#define CLK_TOP_NNA2PLL_D4 126146#define CLK_TOP_NNA2PLL_D8 127147#define CLK_TOP_F_BIST2FPC 128148#define CLK_TOP_466M_FMEM 129149#define CLK_TOP_MPLL 130150#define CLK_TOP_APLL12_CK_DIV0 131151#define CLK_TOP_APLL12_CK_DIV1 132152#define CLK_TOP_APLL12_CK_DIV2 133153#define CLK_TOP_APLL12_CK_DIV4 134154#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M 135155#define CLK_TOP_NR_CLK 136156 157/* INFRACFG_AO */158 159#define CLK_INFRA_AO_PMIC_TMR 0160#define CLK_INFRA_AO_PMIC_AP 1161#define CLK_INFRA_AO_PMIC_MD 2162#define CLK_INFRA_AO_PMIC_CONN 3163#define CLK_INFRA_AO_SCP_CORE 4164#define CLK_INFRA_AO_SEJ 5165#define CLK_INFRA_AO_APXGPT 6166#define CLK_INFRA_AO_ICUSB 7167#define CLK_INFRA_AO_GCE 8168#define CLK_INFRA_AO_THERM 9169#define CLK_INFRA_AO_I2C_AP 10170#define CLK_INFRA_AO_I2C_CCU 11171#define CLK_INFRA_AO_I2C_SSPM 12172#define CLK_INFRA_AO_I2C_RSV 13173#define CLK_INFRA_AO_PWM_HCLK 14174#define CLK_INFRA_AO_PWM1 15175#define CLK_INFRA_AO_PWM2 16176#define CLK_INFRA_AO_PWM3 17177#define CLK_INFRA_AO_PWM4 18178#define CLK_INFRA_AO_PWM5 19179#define CLK_INFRA_AO_PWM 20180#define CLK_INFRA_AO_UART0 21181#define CLK_INFRA_AO_UART1 22182#define CLK_INFRA_AO_UART2 23183#define CLK_INFRA_AO_GCE_26M 24184#define CLK_INFRA_AO_CQ_DMA_FPC 25185#define CLK_INFRA_AO_BTIF 26186#define CLK_INFRA_AO_SPI0 27187#define CLK_INFRA_AO_MSDC0 28188#define CLK_INFRA_AO_MSDCFDE 29189#define CLK_INFRA_AO_MSDC1 30190#define CLK_INFRA_AO_DVFSRC 31191#define CLK_INFRA_AO_GCPU 32192#define CLK_INFRA_AO_TRNG 33193#define CLK_INFRA_AO_AUXADC 34194#define CLK_INFRA_AO_CPUM 35195#define CLK_INFRA_AO_CCIF1_AP 36196#define CLK_INFRA_AO_CCIF1_MD 37197#define CLK_INFRA_AO_AUXADC_MD 38198#define CLK_INFRA_AO_AP_DMA 39199#define CLK_INFRA_AO_XIU 40200#define CLK_INFRA_AO_DEVICE_APC 41201#define CLK_INFRA_AO_CCIF_AP 42202#define CLK_INFRA_AO_DEBUGTOP 43203#define CLK_INFRA_AO_AUDIO 44204#define CLK_INFRA_AO_CCIF_MD 45205#define CLK_INFRA_AO_DXCC_SEC_CORE 46206#define CLK_INFRA_AO_DXCC_AO 47207#define CLK_INFRA_AO_IMP_IIC 48208#define CLK_INFRA_AO_DRAMC_F26M 49209#define CLK_INFRA_AO_RG_PWM_FBCLK6 50210#define CLK_INFRA_AO_SSUSB_TOP_HCLK 51211#define CLK_INFRA_AO_DISP_PWM 52212#define CLK_INFRA_AO_CLDMA_BCLK 53213#define CLK_INFRA_AO_AUDIO_26M_BCLK 54214#define CLK_INFRA_AO_SSUSB_TOP_P1_HCLK 55215#define CLK_INFRA_AO_SPI1 56216#define CLK_INFRA_AO_I2C4 57217#define CLK_INFRA_AO_MODEM_TEMP_SHARE 58218#define CLK_INFRA_AO_SPI2 59219#define CLK_INFRA_AO_SPI3 60220#define CLK_INFRA_AO_SSUSB_TOP_REF 61221#define CLK_INFRA_AO_SSUSB_TOP_XHCI 62222#define CLK_INFRA_AO_SSUSB_TOP_P1_REF 63223#define CLK_INFRA_AO_SSUSB_TOP_P1_XHCI 64224#define CLK_INFRA_AO_SSPM 65225#define CLK_INFRA_AO_SSUSB_TOP_P1_SYS 66226#define CLK_INFRA_AO_I2C5 67227#define CLK_INFRA_AO_I2C5_ARBITER 68228#define CLK_INFRA_AO_I2C5_IMM 69229#define CLK_INFRA_AO_I2C1_ARBITER 70230#define CLK_INFRA_AO_I2C1_IMM 71231#define CLK_INFRA_AO_I2C2_ARBITER 72232#define CLK_INFRA_AO_I2C2_IMM 73233#define CLK_INFRA_AO_SPI4 74234#define CLK_INFRA_AO_SPI5 75235#define CLK_INFRA_AO_CQ_DMA 76236#define CLK_INFRA_AO_BIST2FPC 77237#define CLK_INFRA_AO_MSDC0_SELF 78238#define CLK_INFRA_AO_SPINOR 79239#define CLK_INFRA_AO_SSPM_26M_SELF 80240#define CLK_INFRA_AO_SSPM_32K_SELF 81241#define CLK_INFRA_AO_I2C6 82242#define CLK_INFRA_AO_AP_MSDC0 83243#define CLK_INFRA_AO_MD_MSDC0 84244#define CLK_INFRA_AO_MSDC0_SRC 85245#define CLK_INFRA_AO_MSDC1_SRC 86246#define CLK_INFRA_AO_SEJ_F13M 87247#define CLK_INFRA_AO_AES_TOP0_BCLK 88248#define CLK_INFRA_AO_MCU_PM_BCLK 89249#define CLK_INFRA_AO_CCIF2_AP 90250#define CLK_INFRA_AO_CCIF2_MD 91251#define CLK_INFRA_AO_CCIF3_AP 92252#define CLK_INFRA_AO_CCIF3_MD 93253#define CLK_INFRA_AO_FADSP_26M 94254#define CLK_INFRA_AO_FADSP_32K 95255#define CLK_INFRA_AO_CCIF4_AP 96256#define CLK_INFRA_AO_CCIF4_MD 97257#define CLK_INFRA_AO_FADSP 98258#define CLK_INFRA_AO_FLASHIF_133M 99259#define CLK_INFRA_AO_FLASHIF_66M 100260#define CLK_INFRA_AO_NR_CLK 101261 262/* APMIXEDSYS */263 264#define CLK_APMIXED_ARMPLL_LL 0265#define CLK_APMIXED_ARMPLL_BL 1266#define CLK_APMIXED_CCIPLL 2267#define CLK_APMIXED_MAINPLL 3268#define CLK_APMIXED_UNIV2PLL 4269#define CLK_APMIXED_MSDCPLL 5270#define CLK_APMIXED_MMPLL 6271#define CLK_APMIXED_NNAPLL 7272#define CLK_APMIXED_NNA2PLL 8273#define CLK_APMIXED_ADSPPLL 9274#define CLK_APMIXED_MFGPLL 10275#define CLK_APMIXED_TVDPLL 11276#define CLK_APMIXED_APLL1 12277#define CLK_APMIXED_APLL2 13278#define CLK_APMIXED_NR_CLK 14279 280/* IMP_IIC_WRAP */281 282#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0 0283#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1 1284#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2 2285#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3 3286#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4 4287#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5 5288#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6 6289#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7 7290#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8 8291#define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9 9292#define CLK_IMP_IIC_WRAP_NR_CLK 10293 294/* MFGCFG */295 296#define CLK_MFG_BG3D 0297#define CLK_MFG_NR_CLK 1298 299/* MMSYS */300 301#define CLK_MM_DISP_MUTEX0 0302#define CLK_MM_APB_MM_BUS 1303#define CLK_MM_DISP_OVL0 2304#define CLK_MM_DISP_RDMA0 3305#define CLK_MM_DISP_OVL0_2L 4306#define CLK_MM_DISP_WDMA0 5307#define CLK_MM_DISP_RSZ0 6308#define CLK_MM_DISP_AAL0 7309#define CLK_MM_DISP_CCORR0 8310#define CLK_MM_DISP_COLOR0 9311#define CLK_MM_SMI_INFRA 10312#define CLK_MM_DISP_DSC_WRAP0 11313#define CLK_MM_DISP_GAMMA0 12314#define CLK_MM_DISP_POSTMASK0 13315#define CLK_MM_DISP_DITHER0 14316#define CLK_MM_SMI_COMMON 15317#define CLK_MM_DSI0 16318#define CLK_MM_DISP_FAKE_ENG0 17319#define CLK_MM_DISP_FAKE_ENG1 18320#define CLK_MM_SMI_GALS 19321#define CLK_MM_SMI_IOMMU 20322#define CLK_MM_DISP_RDMA1 21323#define CLK_MM_DISP_DPI 22324#define CLK_MM_DSI0_DSI_CK_DOMAIN 23325#define CLK_MM_DISP_26M 24326#define CLK_MM_NR_CLK 25327 328/* WPESYS */329 330#define CLK_WPE_CK_EN 0331#define CLK_WPE_SMI_LARB8_CK_EN 1332#define CLK_WPE_SYS_EVENT_TX_CK_EN 2333#define CLK_WPE_SMI_LARB8_PCLK_EN 3334#define CLK_WPE_NR_CLK 4335 336/* IMGSYS1 */337 338#define CLK_IMG1_LARB9_IMG1 0339#define CLK_IMG1_LARB10_IMG1 1340#define CLK_IMG1_DIP 2341#define CLK_IMG1_GALS_IMG1 3342#define CLK_IMG1_NR_CLK 4343 344/* IMGSYS2 */345 346#define CLK_IMG2_LARB9_IMG2 0347#define CLK_IMG2_LARB10_IMG2 1348#define CLK_IMG2_MFB 2349#define CLK_IMG2_WPE 3350#define CLK_IMG2_MSS 4351#define CLK_IMG2_GALS_IMG2 5352#define CLK_IMG2_NR_CLK 6353 354/* VDECSYS */355 356#define CLK_VDEC_LARB1_CKEN 0357#define CLK_VDEC_LAT_CKEN 1358#define CLK_VDEC_LAT_ACTIVE 2359#define CLK_VDEC_LAT_CKEN_ENG 3360#define CLK_VDEC_MINI_MDP_CKEN_CFG_RG 4361#define CLK_VDEC_CKEN 5362#define CLK_VDEC_ACTIVE 6363#define CLK_VDEC_CKEN_ENG 7364#define CLK_VDEC_NR_CLK 8365 366/* VENCSYS */367 368#define CLK_VENC_CKE0_LARB 0369#define CLK_VENC_CKE1_VENC 1370#define CLK_VENC_CKE2_JPGENC 2371#define CLK_VENC_CKE5_GALS 3372#define CLK_VENC_NR_CLK 4373 374/* CAMSYS */375 376#define CLK_CAM_LARB13 0377#define CLK_CAM_DFP_VAD 1378#define CLK_CAM_LARB14 2379#define CLK_CAM 3380#define CLK_CAMTG 4381#define CLK_CAM_SENINF 5382#define CLK_CAMSV1 6383#define CLK_CAMSV2 7384#define CLK_CAMSV3 8385#define CLK_CAM_CCU0 9386#define CLK_CAM_CCU1 10387#define CLK_CAM_MRAW0 11388#define CLK_CAM_FAKE_ENG 12389#define CLK_CAM_CCU_GALS 13390#define CLK_CAM2MM_GALS 14391#define CLK_CAM_NR_CLK 15392 393/* CAMSYS_RAWA */394 395#define CLK_CAM_RAWA_LARBX_RAWA 0396#define CLK_CAM_RAWA 1397#define CLK_CAM_RAWA_CAMTG_RAWA 2398#define CLK_CAM_RAWA_NR_CLK 3399 400/* CAMSYS_RAWB */401 402#define CLK_CAM_RAWB_LARBX_RAWB 0403#define CLK_CAM_RAWB 1404#define CLK_CAM_RAWB_CAMTG_RAWB 2405#define CLK_CAM_RAWB_NR_CLK 3406 407/* MDPSYS */408 409#define CLK_MDP_RDMA0 0410#define CLK_MDP_TDSHP0 1411#define CLK_MDP_IMG_DL_ASYNC0 2412#define CLK_MDP_IMG_DL_ASYNC1 3413#define CLK_MDP_DISP_RDMA 4414#define CLK_MDP_HMS 5415#define CLK_MDP_SMI0 6416#define CLK_MDP_APB_BUS 7417#define CLK_MDP_WROT0 8418#define CLK_MDP_RSZ0 9419#define CLK_MDP_HDR0 10420#define CLK_MDP_MUTEX0 11421#define CLK_MDP_WROT1 12422#define CLK_MDP_RSZ1 13423#define CLK_MDP_FAKE_ENG0 14424#define CLK_MDP_AAL0 15425#define CLK_MDP_DISP_WDMA 16426#define CLK_MDP_COLOR 17427#define CLK_MDP_IMG_DL_ASYNC2 18428#define CLK_MDP_IMG_DL_RELAY0_ASYNC0 19429#define CLK_MDP_IMG_DL_RELAY1_ASYNC1 20430#define CLK_MDP_IMG_DL_RELAY2_ASYNC2 21431#define CLK_MDP_NR_CLK 22432 433/* IPESYS */434 435#define CLK_IPE_LARB19 0436#define CLK_IPE_LARB20 1437#define CLK_IPE_SMI_SUBCOM 2438#define CLK_IPE_FD 3439#define CLK_IPE_FE 4440#define CLK_IPE_RSC 5441#define CLK_IPE_DPE 6442#define CLK_IPE_GALS_IPE 7443#define CLK_IPE_NR_CLK 8444 445#endif /* _DT_BINDINGS_CLK_MT8186_H */446