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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2021 MediaTek Inc.4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_CLK_MT8192_H8#define _DT_BINDINGS_CLK_MT8192_H9 10/* TOPCKGEN */11 12#define CLK_TOP_AXI_SEL 013#define CLK_TOP_SPM_SEL 114#define CLK_TOP_SCP_SEL 215#define CLK_TOP_BUS_AXIMEM_SEL 316#define CLK_TOP_DISP_SEL 417#define CLK_TOP_MDP_SEL 518#define CLK_TOP_IMG1_SEL 619#define CLK_TOP_IMG2_SEL 720#define CLK_TOP_IPE_SEL 821#define CLK_TOP_DPE_SEL 922#define CLK_TOP_CAM_SEL 1023#define CLK_TOP_CCU_SEL 1124#define CLK_TOP_DSP7_SEL 1225#define CLK_TOP_MFG_REF_SEL 1326#define CLK_TOP_MFG_PLL_SEL 1427#define CLK_TOP_CAMTG_SEL 1528#define CLK_TOP_CAMTG2_SEL 1629#define CLK_TOP_CAMTG3_SEL 1730#define CLK_TOP_CAMTG4_SEL 1831#define CLK_TOP_CAMTG5_SEL 1932#define CLK_TOP_CAMTG6_SEL 2033#define CLK_TOP_UART_SEL 2134#define CLK_TOP_SPI_SEL 2235#define CLK_TOP_MSDC50_0_H_SEL 2336#define CLK_TOP_MSDC50_0_SEL 2437#define CLK_TOP_MSDC30_1_SEL 2538#define CLK_TOP_MSDC30_2_SEL 2639#define CLK_TOP_AUDIO_SEL 2740#define CLK_TOP_AUD_INTBUS_SEL 2841#define CLK_TOP_PWRAP_ULPOSC_SEL 2942#define CLK_TOP_ATB_SEL 3043#define CLK_TOP_DPI_SEL 3144#define CLK_TOP_SCAM_SEL 3245#define CLK_TOP_DISP_PWM_SEL 3346#define CLK_TOP_USB_TOP_SEL 3447#define CLK_TOP_SSUSB_XHCI_SEL 3548#define CLK_TOP_I2C_SEL 3649#define CLK_TOP_SENINF_SEL 3750#define CLK_TOP_SENINF1_SEL 3851#define CLK_TOP_SENINF2_SEL 3952#define CLK_TOP_SENINF3_SEL 4053#define CLK_TOP_TL_SEL 4154#define CLK_TOP_DXCC_SEL 4255#define CLK_TOP_AUD_ENGEN1_SEL 4356#define CLK_TOP_AUD_ENGEN2_SEL 4457#define CLK_TOP_AES_UFSFDE_SEL 4558#define CLK_TOP_UFS_SEL 4659#define CLK_TOP_AUD_1_SEL 4760#define CLK_TOP_AUD_2_SEL 4861#define CLK_TOP_ADSP_SEL 4962#define CLK_TOP_DPMAIF_MAIN_SEL 5063#define CLK_TOP_VENC_SEL 5164#define CLK_TOP_VDEC_SEL 5265#define CLK_TOP_CAMTM_SEL 5366#define CLK_TOP_PWM_SEL 5467#define CLK_TOP_AUDIO_H_SEL 5568#define CLK_TOP_SPMI_MST_SEL 5669#define CLK_TOP_AES_MSDCFDE_SEL 5770#define CLK_TOP_SFLASH_SEL 5871#define CLK_TOP_APLL_I2S0_M_SEL 5972#define CLK_TOP_APLL_I2S1_M_SEL 6073#define CLK_TOP_APLL_I2S2_M_SEL 6174#define CLK_TOP_APLL_I2S3_M_SEL 6275#define CLK_TOP_APLL_I2S4_M_SEL 6376#define CLK_TOP_APLL_I2S5_M_SEL 6477#define CLK_TOP_APLL_I2S6_M_SEL 6578#define CLK_TOP_APLL_I2S7_M_SEL 6679#define CLK_TOP_APLL_I2S8_M_SEL 6780#define CLK_TOP_APLL_I2S9_M_SEL 6881#define CLK_TOP_MAINPLL_D3 6982#define CLK_TOP_MAINPLL_D4 7083#define CLK_TOP_MAINPLL_D4_D2 7184#define CLK_TOP_MAINPLL_D4_D4 7285#define CLK_TOP_MAINPLL_D4_D8 7386#define CLK_TOP_MAINPLL_D4_D16 7487#define CLK_TOP_MAINPLL_D5 7588#define CLK_TOP_MAINPLL_D5_D2 7689#define CLK_TOP_MAINPLL_D5_D4 7790#define CLK_TOP_MAINPLL_D5_D8 7891#define CLK_TOP_MAINPLL_D6 7992#define CLK_TOP_MAINPLL_D6_D2 8093#define CLK_TOP_MAINPLL_D6_D4 8194#define CLK_TOP_MAINPLL_D7 8295#define CLK_TOP_MAINPLL_D7_D2 8396#define CLK_TOP_MAINPLL_D7_D4 8497#define CLK_TOP_MAINPLL_D7_D8 8598#define CLK_TOP_UNIVPLL_D3 8699#define CLK_TOP_UNIVPLL_D4 87100#define CLK_TOP_UNIVPLL_D4_D2 88101#define CLK_TOP_UNIVPLL_D4_D4 89102#define CLK_TOP_UNIVPLL_D4_D8 90103#define CLK_TOP_UNIVPLL_D5 91104#define CLK_TOP_UNIVPLL_D5_D2 92105#define CLK_TOP_UNIVPLL_D5_D4 93106#define CLK_TOP_UNIVPLL_D5_D8 94107#define CLK_TOP_UNIVPLL_D6 95108#define CLK_TOP_UNIVPLL_D6_D2 96109#define CLK_TOP_UNIVPLL_D6_D4 97110#define CLK_TOP_UNIVPLL_D6_D8 98111#define CLK_TOP_UNIVPLL_D6_D16 99112#define CLK_TOP_UNIVPLL_D7 100113#define CLK_TOP_APLL1 101114#define CLK_TOP_APLL1_D2 102115#define CLK_TOP_APLL1_D4 103116#define CLK_TOP_APLL1_D8 104117#define CLK_TOP_APLL2 105118#define CLK_TOP_APLL2_D2 106119#define CLK_TOP_APLL2_D4 107120#define CLK_TOP_APLL2_D8 108121#define CLK_TOP_MMPLL_D4 109122#define CLK_TOP_MMPLL_D4_D2 110123#define CLK_TOP_MMPLL_D5 111124#define CLK_TOP_MMPLL_D5_D2 112125#define CLK_TOP_MMPLL_D6 113126#define CLK_TOP_MMPLL_D6_D2 114127#define CLK_TOP_MMPLL_D7 115128#define CLK_TOP_MMPLL_D9 116129#define CLK_TOP_APUPLL 117130#define CLK_TOP_NPUPLL 118131#define CLK_TOP_TVDPLL 119132#define CLK_TOP_TVDPLL_D2 120133#define CLK_TOP_TVDPLL_D4 121134#define CLK_TOP_TVDPLL_D8 122135#define CLK_TOP_TVDPLL_D16 123136#define CLK_TOP_MSDCPLL 124137#define CLK_TOP_MSDCPLL_D2 125138#define CLK_TOP_MSDCPLL_D4 126139#define CLK_TOP_ULPOSC 127140#define CLK_TOP_OSC_D2 128141#define CLK_TOP_OSC_D4 129142#define CLK_TOP_OSC_D8 130143#define CLK_TOP_OSC_D10 131144#define CLK_TOP_OSC_D16 132145#define CLK_TOP_OSC_D20 133146#define CLK_TOP_CSW_F26M_D2 134147#define CLK_TOP_ADSPPLL 135148#define CLK_TOP_UNIVPLL_192M 136149#define CLK_TOP_UNIVPLL_192M_D2 137150#define CLK_TOP_UNIVPLL_192M_D4 138151#define CLK_TOP_UNIVPLL_192M_D8 139152#define CLK_TOP_UNIVPLL_192M_D16 140153#define CLK_TOP_UNIVPLL_192M_D32 141154#define CLK_TOP_APLL12_DIV0 142155#define CLK_TOP_APLL12_DIV1 143156#define CLK_TOP_APLL12_DIV2 144157#define CLK_TOP_APLL12_DIV3 145158#define CLK_TOP_APLL12_DIV4 146159#define CLK_TOP_APLL12_DIVB 147160#define CLK_TOP_APLL12_DIV5 148161#define CLK_TOP_APLL12_DIV6 149162#define CLK_TOP_APLL12_DIV7 150163#define CLK_TOP_APLL12_DIV8 151164#define CLK_TOP_APLL12_DIV9 152165#define CLK_TOP_SSUSB_TOP_REF 153166#define CLK_TOP_SSUSB_PHY_REF 154167#define CLK_TOP_NR_CLK 155168 169/* INFRACFG */170 171#define CLK_INFRA_PMIC_TMR 0172#define CLK_INFRA_PMIC_AP 1173#define CLK_INFRA_PMIC_MD 2174#define CLK_INFRA_PMIC_CONN 3175#define CLK_INFRA_SCPSYS 4176#define CLK_INFRA_SEJ 5177#define CLK_INFRA_APXGPT 6178#define CLK_INFRA_GCE 7179#define CLK_INFRA_GCE2 8180#define CLK_INFRA_THERM 9181#define CLK_INFRA_I2C0 10182#define CLK_INFRA_AP_DMA_PSEUDO 11183#define CLK_INFRA_I2C2 12184#define CLK_INFRA_I2C3 13185#define CLK_INFRA_PWM_H 14186#define CLK_INFRA_PWM1 15187#define CLK_INFRA_PWM2 16188#define CLK_INFRA_PWM3 17189#define CLK_INFRA_PWM4 18190#define CLK_INFRA_PWM 19191#define CLK_INFRA_UART0 20192#define CLK_INFRA_UART1 21193#define CLK_INFRA_UART2 22194#define CLK_INFRA_UART3 23195#define CLK_INFRA_GCE_26M 24196#define CLK_INFRA_CQ_DMA_FPC 25197#define CLK_INFRA_BTIF 26198#define CLK_INFRA_SPI0 27199#define CLK_INFRA_MSDC0 28200#define CLK_INFRA_MSDC1 29201#define CLK_INFRA_MSDC2 30202#define CLK_INFRA_MSDC0_SRC 31203#define CLK_INFRA_GCPU 32204#define CLK_INFRA_TRNG 33205#define CLK_INFRA_AUXADC 34206#define CLK_INFRA_CPUM 35207#define CLK_INFRA_CCIF1_AP 36208#define CLK_INFRA_CCIF1_MD 37209#define CLK_INFRA_AUXADC_MD 38210#define CLK_INFRA_PCIE_TL_26M 39211#define CLK_INFRA_MSDC1_SRC 40212#define CLK_INFRA_MSDC2_SRC 41213#define CLK_INFRA_PCIE_TL_96M 42214#define CLK_INFRA_PCIE_PL_P_250M 43215#define CLK_INFRA_DEVICE_APC 44216#define CLK_INFRA_CCIF_AP 45217#define CLK_INFRA_DEBUGSYS 46218#define CLK_INFRA_AUDIO 47219#define CLK_INFRA_CCIF_MD 48220#define CLK_INFRA_DXCC_SEC_CORE 49221#define CLK_INFRA_DXCC_AO 50222#define CLK_INFRA_DBG_TRACE 51223#define CLK_INFRA_DEVMPU_B 52224#define CLK_INFRA_DRAMC_F26M 53225#define CLK_INFRA_IRTX 54226#define CLK_INFRA_SSUSB 55227#define CLK_INFRA_DISP_PWM 56228#define CLK_INFRA_CLDMA_B 57229#define CLK_INFRA_AUDIO_26M_B 58230#define CLK_INFRA_MODEM_TEMP_SHARE 59231#define CLK_INFRA_SPI1 60232#define CLK_INFRA_I2C4 61233#define CLK_INFRA_SPI2 62234#define CLK_INFRA_SPI3 63235#define CLK_INFRA_UNIPRO_SYS 64236#define CLK_INFRA_UNIPRO_TICK 65237#define CLK_INFRA_UFS_MP_SAP_B 66238#define CLK_INFRA_MD32_B 67239#define CLK_INFRA_UNIPRO_MBIST 68240#define CLK_INFRA_I2C5 69241#define CLK_INFRA_I2C5_ARBITER 70242#define CLK_INFRA_I2C5_IMM 71243#define CLK_INFRA_I2C1_ARBITER 72244#define CLK_INFRA_I2C1_IMM 73245#define CLK_INFRA_I2C2_ARBITER 74246#define CLK_INFRA_I2C2_IMM 75247#define CLK_INFRA_SPI4 76248#define CLK_INFRA_SPI5 77249#define CLK_INFRA_CQ_DMA 78250#define CLK_INFRA_UFS 79251#define CLK_INFRA_AES_UFSFDE 80252#define CLK_INFRA_UFS_TICK 81253#define CLK_INFRA_SSUSB_XHCI 82254#define CLK_INFRA_MSDC0_SELF 83255#define CLK_INFRA_MSDC1_SELF 84256#define CLK_INFRA_MSDC2_SELF 85257#define CLK_INFRA_UFS_AXI 86258#define CLK_INFRA_I2C6 87259#define CLK_INFRA_AP_MSDC0 88260#define CLK_INFRA_MD_MSDC0 89261#define CLK_INFRA_CCIF5_AP 90262#define CLK_INFRA_CCIF5_MD 91263#define CLK_INFRA_PCIE_TOP_H_133M 92264#define CLK_INFRA_FLASHIF_TOP_H_133M 93265#define CLK_INFRA_PCIE_PERI_26M 94266#define CLK_INFRA_CCIF2_AP 95267#define CLK_INFRA_CCIF2_MD 96268#define CLK_INFRA_CCIF3_AP 97269#define CLK_INFRA_CCIF3_MD 98270#define CLK_INFRA_SEJ_F13M 99271#define CLK_INFRA_AES 100272#define CLK_INFRA_I2C7 101273#define CLK_INFRA_I2C8 102274#define CLK_INFRA_FBIST2FPC 103275#define CLK_INFRA_DEVICE_APC_SYNC 104276#define CLK_INFRA_DPMAIF_MAIN 105277#define CLK_INFRA_PCIE_TL_32K 106278#define CLK_INFRA_CCIF4_AP 107279#define CLK_INFRA_CCIF4_MD 108280#define CLK_INFRA_SPI6 109281#define CLK_INFRA_SPI7 110282#define CLK_INFRA_133M 111283#define CLK_INFRA_66M 112284#define CLK_INFRA_66M_PERI_BUS 113285#define CLK_INFRA_FREE_DCM_133M 114286#define CLK_INFRA_FREE_DCM_66M 115287#define CLK_INFRA_PERI_BUS_DCM_133M 116288#define CLK_INFRA_PERI_BUS_DCM_66M 117289#define CLK_INFRA_FLASHIF_PERI_26M 118290#define CLK_INFRA_FLASHIF_SFLASH 119291#define CLK_INFRA_AP_DMA 120292#define CLK_INFRA_NR_CLK 121293 294/* PERICFG */295 296#define CLK_PERI_PERIAXI 0297#define CLK_PERI_NR_CLK 1298 299/* APMIXEDSYS */300 301#define CLK_APMIXED_MAINPLL 0302#define CLK_APMIXED_UNIVPLL 1303#define CLK_APMIXED_USBPLL 2304#define CLK_APMIXED_MSDCPLL 3305#define CLK_APMIXED_MMPLL 4306#define CLK_APMIXED_ADSPPLL 5307#define CLK_APMIXED_MFGPLL 6308#define CLK_APMIXED_TVDPLL 7309#define CLK_APMIXED_APLL1 8310#define CLK_APMIXED_APLL2 9311#define CLK_APMIXED_MIPID26M 10312#define CLK_APMIXED_NR_CLK 11313 314/* SCP_ADSP */315 316#define CLK_SCP_ADSP_AUDIODSP 0317#define CLK_SCP_ADSP_NR_CLK 1318 319/* IMP_IIC_WRAP_C */320 321#define CLK_IMP_IIC_WRAP_C_I2C10 0322#define CLK_IMP_IIC_WRAP_C_I2C11 1323#define CLK_IMP_IIC_WRAP_C_I2C12 2324#define CLK_IMP_IIC_WRAP_C_I2C13 3325#define CLK_IMP_IIC_WRAP_C_NR_CLK 4326 327/* AUDSYS */328 329#define CLK_AUD_AFE 0330#define CLK_AUD_22M 1331#define CLK_AUD_24M 2332#define CLK_AUD_APLL2_TUNER 3333#define CLK_AUD_APLL_TUNER 4334#define CLK_AUD_TDM 5335#define CLK_AUD_ADC 6336#define CLK_AUD_DAC 7337#define CLK_AUD_DAC_PREDIS 8338#define CLK_AUD_TML 9339#define CLK_AUD_NLE 10340#define CLK_AUD_I2S1_B 11341#define CLK_AUD_I2S2_B 12342#define CLK_AUD_I2S3_B 13343#define CLK_AUD_I2S4_B 14344#define CLK_AUD_CONNSYS_I2S_ASRC 15345#define CLK_AUD_GENERAL1_ASRC 16346#define CLK_AUD_GENERAL2_ASRC 17347#define CLK_AUD_DAC_HIRES 18348#define CLK_AUD_ADC_HIRES 19349#define CLK_AUD_ADC_HIRES_TML 20350#define CLK_AUD_ADDA6_ADC 21351#define CLK_AUD_ADDA6_ADC_HIRES 22352#define CLK_AUD_3RD_DAC 23353#define CLK_AUD_3RD_DAC_PREDIS 24354#define CLK_AUD_3RD_DAC_TML 25355#define CLK_AUD_3RD_DAC_HIRES 26356#define CLK_AUD_I2S5_B 27357#define CLK_AUD_I2S6_B 28358#define CLK_AUD_I2S7_B 29359#define CLK_AUD_I2S8_B 30360#define CLK_AUD_I2S9_B 31361#define CLK_AUD_NR_CLK 32362 363/* IMP_IIC_WRAP_E */364 365#define CLK_IMP_IIC_WRAP_E_I2C3 0366#define CLK_IMP_IIC_WRAP_E_NR_CLK 1367 368/* IMP_IIC_WRAP_S */369 370#define CLK_IMP_IIC_WRAP_S_I2C7 0371#define CLK_IMP_IIC_WRAP_S_I2C8 1372#define CLK_IMP_IIC_WRAP_S_I2C9 2373#define CLK_IMP_IIC_WRAP_S_NR_CLK 3374 375/* IMP_IIC_WRAP_WS */376 377#define CLK_IMP_IIC_WRAP_WS_I2C1 0378#define CLK_IMP_IIC_WRAP_WS_I2C2 1379#define CLK_IMP_IIC_WRAP_WS_I2C4 2380#define CLK_IMP_IIC_WRAP_WS_NR_CLK 3381 382/* IMP_IIC_WRAP_W */383 384#define CLK_IMP_IIC_WRAP_W_I2C5 0385#define CLK_IMP_IIC_WRAP_W_NR_CLK 1386 387/* IMP_IIC_WRAP_N */388 389#define CLK_IMP_IIC_WRAP_N_I2C0 0390#define CLK_IMP_IIC_WRAP_N_I2C6 1391#define CLK_IMP_IIC_WRAP_N_NR_CLK 2392 393/* MSDC_TOP */394 395#define CLK_MSDC_TOP_AES_0P 0396#define CLK_MSDC_TOP_SRC_0P 1397#define CLK_MSDC_TOP_SRC_1P 2398#define CLK_MSDC_TOP_SRC_2P 3399#define CLK_MSDC_TOP_P_MSDC0 4400#define CLK_MSDC_TOP_P_MSDC1 5401#define CLK_MSDC_TOP_P_MSDC2 6402#define CLK_MSDC_TOP_P_CFG 7403#define CLK_MSDC_TOP_AXI 8404#define CLK_MSDC_TOP_H_MST_0P 9405#define CLK_MSDC_TOP_H_MST_1P 10406#define CLK_MSDC_TOP_H_MST_2P 11407#define CLK_MSDC_TOP_MEM_OFF_DLY_26M 12408#define CLK_MSDC_TOP_32K 13409#define CLK_MSDC_TOP_AHB2AXI_BRG_AXI 14410#define CLK_MSDC_TOP_NR_CLK 15411 412/* MSDC */413 414#define CLK_MSDC_AXI_WRAP 0415#define CLK_MSDC_NR_CLK 1416 417/* MFGCFG */418 419#define CLK_MFG_BG3D 0420#define CLK_MFG_NR_CLK 1421 422/* MMSYS */423 424#define CLK_MM_DISP_MUTEX0 0425#define CLK_MM_DISP_CONFIG 1426#define CLK_MM_DISP_OVL0 2427#define CLK_MM_DISP_RDMA0 3428#define CLK_MM_DISP_OVL0_2L 4429#define CLK_MM_DISP_WDMA0 5430#define CLK_MM_DISP_UFBC_WDMA0 6431#define CLK_MM_DISP_RSZ0 7432#define CLK_MM_DISP_AAL0 8433#define CLK_MM_DISP_CCORR0 9434#define CLK_MM_DISP_DITHER0 10435#define CLK_MM_SMI_INFRA 11436#define CLK_MM_DISP_GAMMA0 12437#define CLK_MM_DISP_POSTMASK0 13438#define CLK_MM_DISP_DSC_WRAP0 14439#define CLK_MM_DSI0 15440#define CLK_MM_DISP_COLOR0 16441#define CLK_MM_SMI_COMMON 17442#define CLK_MM_DISP_FAKE_ENG0 18443#define CLK_MM_DISP_FAKE_ENG1 19444#define CLK_MM_MDP_TDSHP4 20445#define CLK_MM_MDP_RSZ4 21446#define CLK_MM_MDP_AAL4 22447#define CLK_MM_MDP_HDR4 23448#define CLK_MM_MDP_RDMA4 24449#define CLK_MM_MDP_COLOR4 25450#define CLK_MM_DISP_Y2R0 26451#define CLK_MM_SMI_GALS 27452#define CLK_MM_DISP_OVL2_2L 28453#define CLK_MM_DISP_RDMA4 29454#define CLK_MM_DISP_DPI0 30455#define CLK_MM_SMI_IOMMU 31456#define CLK_MM_DSI_DSI0 32457#define CLK_MM_DPI_DPI0 33458#define CLK_MM_26MHZ 34459#define CLK_MM_32KHZ 35460#define CLK_MM_NR_CLK 36461 462/* IMGSYS */463 464#define CLK_IMG_LARB9 0465#define CLK_IMG_LARB10 1466#define CLK_IMG_DIP 2467#define CLK_IMG_GALS 3468#define CLK_IMG_NR_CLK 4469 470/* IMGSYS2 */471 472#define CLK_IMG2_LARB11 0473#define CLK_IMG2_LARB12 1474#define CLK_IMG2_MFB 2475#define CLK_IMG2_WPE 3476#define CLK_IMG2_MSS 4477#define CLK_IMG2_GALS 5478#define CLK_IMG2_NR_CLK 6479 480/* VDECSYS_SOC */481 482#define CLK_VDEC_SOC_LARB1 0483#define CLK_VDEC_SOC_LAT 1484#define CLK_VDEC_SOC_LAT_ACTIVE 2485#define CLK_VDEC_SOC_VDEC 3486#define CLK_VDEC_SOC_VDEC_ACTIVE 4487#define CLK_VDEC_SOC_NR_CLK 5488 489/* VDECSYS */490 491#define CLK_VDEC_LARB1 0492#define CLK_VDEC_LAT 1493#define CLK_VDEC_LAT_ACTIVE 2494#define CLK_VDEC_VDEC 3495#define CLK_VDEC_ACTIVE 4496#define CLK_VDEC_NR_CLK 5497 498/* VENCSYS */499 500#define CLK_VENC_SET0_LARB 0501#define CLK_VENC_SET1_VENC 1502#define CLK_VENC_SET2_JPGENC 2503#define CLK_VENC_SET5_GALS 3504#define CLK_VENC_NR_CLK 4505 506/* CAMSYS */507 508#define CLK_CAM_LARB13 0509#define CLK_CAM_DFP_VAD 1510#define CLK_CAM_LARB14 2511#define CLK_CAM_CAM 3512#define CLK_CAM_CAMTG 4513#define CLK_CAM_SENINF 5514#define CLK_CAM_CAMSV0 6515#define CLK_CAM_CAMSV1 7516#define CLK_CAM_CAMSV2 8517#define CLK_CAM_CAMSV3 9518#define CLK_CAM_CCU0 10519#define CLK_CAM_CCU1 11520#define CLK_CAM_MRAW0 12521#define CLK_CAM_FAKE_ENG 13522#define CLK_CAM_CCU_GALS 14523#define CLK_CAM_CAM2MM_GALS 15524#define CLK_CAM_NR_CLK 16525 526/* CAMSYS_RAWA */527 528#define CLK_CAM_RAWA_LARBX 0529#define CLK_CAM_RAWA_CAM 1530#define CLK_CAM_RAWA_CAMTG 2531#define CLK_CAM_RAWA_NR_CLK 3532 533/* CAMSYS_RAWB */534 535#define CLK_CAM_RAWB_LARBX 0536#define CLK_CAM_RAWB_CAM 1537#define CLK_CAM_RAWB_CAMTG 2538#define CLK_CAM_RAWB_NR_CLK 3539 540/* CAMSYS_RAWC */541 542#define CLK_CAM_RAWC_LARBX 0543#define CLK_CAM_RAWC_CAM 1544#define CLK_CAM_RAWC_CAMTG 2545#define CLK_CAM_RAWC_NR_CLK 3546 547/* IPESYS */548 549#define CLK_IPE_LARB19 0550#define CLK_IPE_LARB20 1551#define CLK_IPE_SMI_SUBCOM 2552#define CLK_IPE_FD 3553#define CLK_IPE_FE 4554#define CLK_IPE_RSC 5555#define CLK_IPE_DPE 6556#define CLK_IPE_GALS 7557#define CLK_IPE_NR_CLK 8558 559/* MDPSYS */560 561#define CLK_MDP_RDMA0 0562#define CLK_MDP_TDSHP0 1563#define CLK_MDP_IMG_DL_ASYNC0 2564#define CLK_MDP_IMG_DL_ASYNC1 3565#define CLK_MDP_RDMA1 4566#define CLK_MDP_TDSHP1 5567#define CLK_MDP_SMI0 6568#define CLK_MDP_APB_BUS 7569#define CLK_MDP_WROT0 8570#define CLK_MDP_RSZ0 9571#define CLK_MDP_HDR0 10572#define CLK_MDP_MUTEX0 11573#define CLK_MDP_WROT1 12574#define CLK_MDP_RSZ1 13575#define CLK_MDP_HDR1 14576#define CLK_MDP_FAKE_ENG0 15577#define CLK_MDP_AAL0 16578#define CLK_MDP_AAL1 17579#define CLK_MDP_COLOR0 18580#define CLK_MDP_COLOR1 19581#define CLK_MDP_IMG_DL_RELAY0_ASYNC0 20582#define CLK_MDP_IMG_DL_RELAY1_ASYNC1 21583#define CLK_MDP_NR_CLK 22584 585#endif /* _DT_BINDINGS_CLK_MT8192_H */586