867 lines · c
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */2/*3 * Copyright (c) 2021 MediaTek Inc.4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>5 */6 7#ifndef _DT_BINDINGS_CLK_MT8195_H8#define _DT_BINDINGS_CLK_MT8195_H9 10/* TOPCKGEN */11 12#define CLK_TOP_AXI 013#define CLK_TOP_SPM 114#define CLK_TOP_SCP 215#define CLK_TOP_BUS_AXIMEM 316#define CLK_TOP_VPP 417#define CLK_TOP_ETHDR 518#define CLK_TOP_IPE 619#define CLK_TOP_CAM 720#define CLK_TOP_CCU 821#define CLK_TOP_IMG 922#define CLK_TOP_CAMTM 1023#define CLK_TOP_DSP 1124#define CLK_TOP_DSP1 1225#define CLK_TOP_DSP2 1326#define CLK_TOP_DSP3 1427#define CLK_TOP_DSP4 1528#define CLK_TOP_DSP5 1629#define CLK_TOP_DSP6 1730#define CLK_TOP_DSP7 1831#define CLK_TOP_IPU_IF 1932#define CLK_TOP_MFG_CORE_TMP 2033#define CLK_TOP_CAMTG 2134#define CLK_TOP_CAMTG2 2235#define CLK_TOP_CAMTG3 2336#define CLK_TOP_CAMTG4 2437#define CLK_TOP_CAMTG5 2538#define CLK_TOP_UART 2639#define CLK_TOP_SPI 2740#define CLK_TOP_SPIS 2841#define CLK_TOP_MSDC50_0_HCLK 2942#define CLK_TOP_MSDC50_0 3043#define CLK_TOP_MSDC30_1 3144#define CLK_TOP_MSDC30_2 3245#define CLK_TOP_INTDIR 3346#define CLK_TOP_AUD_INTBUS 3447#define CLK_TOP_AUDIO_H 3548#define CLK_TOP_PWRAP_ULPOSC 3649#define CLK_TOP_ATB 3750#define CLK_TOP_PWRMCU 3851#define CLK_TOP_DP 3952#define CLK_TOP_EDP 4053#define CLK_TOP_DPI 4154#define CLK_TOP_DISP_PWM0 4255#define CLK_TOP_DISP_PWM1 4356#define CLK_TOP_USB_TOP 4457#define CLK_TOP_SSUSB_XHCI 4558#define CLK_TOP_USB_TOP_1P 4659#define CLK_TOP_SSUSB_XHCI_1P 4760#define CLK_TOP_USB_TOP_2P 4861#define CLK_TOP_SSUSB_XHCI_2P 4962#define CLK_TOP_USB_TOP_3P 5063#define CLK_TOP_SSUSB_XHCI_3P 5164#define CLK_TOP_I2C 5265#define CLK_TOP_SENINF 5366#define CLK_TOP_SENINF1 5467#define CLK_TOP_SENINF2 5568#define CLK_TOP_SENINF3 5669#define CLK_TOP_GCPU 5770#define CLK_TOP_DXCC 5871#define CLK_TOP_DPMAIF_MAIN 5972#define CLK_TOP_AES_UFSFDE 6073#define CLK_TOP_UFS 6174#define CLK_TOP_UFS_TICK1US 6275#define CLK_TOP_UFS_MP_SAP_CFG 6376#define CLK_TOP_VENC 6477#define CLK_TOP_VDEC 6578#define CLK_TOP_PWM 6679#define CLK_TOP_MCUPM 6780#define CLK_TOP_SPMI_P_MST 6881#define CLK_TOP_SPMI_M_MST 6982#define CLK_TOP_DVFSRC 7083#define CLK_TOP_TL 7184#define CLK_TOP_TL_P1 7285#define CLK_TOP_AES_MSDCFDE 7386#define CLK_TOP_DSI_OCC 7487#define CLK_TOP_WPE_VPP 7588#define CLK_TOP_HDCP 7689#define CLK_TOP_HDCP_24M 7790#define CLK_TOP_HD20_DACR_REF_CLK 7891#define CLK_TOP_HD20_HDCP_CCLK 7992#define CLK_TOP_HDMI_XTAL 8093#define CLK_TOP_HDMI_APB 8194#define CLK_TOP_SNPS_ETH_250M 8295#define CLK_TOP_SNPS_ETH_62P4M_PTP 8396#define CLK_TOP_SNPS_ETH_50M_RMII 8497#define CLK_TOP_DGI_OUT 8598#define CLK_TOP_NNA0 8699#define CLK_TOP_NNA1 87100#define CLK_TOP_ADSP 88101#define CLK_TOP_ASM_H 89102#define CLK_TOP_ASM_M 90103#define CLK_TOP_ASM_L 91104#define CLK_TOP_APLL1 92105#define CLK_TOP_APLL2 93106#define CLK_TOP_APLL3 94107#define CLK_TOP_APLL4 95108#define CLK_TOP_APLL5 96109#define CLK_TOP_I2SO1_MCK 97110#define CLK_TOP_I2SO2_MCK 98111#define CLK_TOP_I2SI1_MCK 99112#define CLK_TOP_I2SI2_MCK 100113#define CLK_TOP_DPTX_MCK 101114#define CLK_TOP_AUD_IEC_CLK 102115#define CLK_TOP_A1SYS_HP 103116#define CLK_TOP_A2SYS_HF 104117#define CLK_TOP_A3SYS_HF 105118#define CLK_TOP_A4SYS_HF 106119#define CLK_TOP_SPINFI_BCLK 107120#define CLK_TOP_NFI1X 108121#define CLK_TOP_ECC 109122#define CLK_TOP_AUDIO_LOCAL_BUS 110123#define CLK_TOP_SPINOR 111124#define CLK_TOP_DVIO_DGI_REF 112125#define CLK_TOP_ULPOSC 113126#define CLK_TOP_ULPOSC_CORE 114127#define CLK_TOP_SRCK 115128#define CLK_TOP_MFG_CK_FAST_REF 116129#define CLK_TOP_CLK26M_D2 117130#define CLK_TOP_CLK26M_D52 118131#define CLK_TOP_IN_DGI 119132#define CLK_TOP_IN_DGI_D2 120133#define CLK_TOP_IN_DGI_D4 121134#define CLK_TOP_IN_DGI_D6 122135#define CLK_TOP_IN_DGI_D8 123136#define CLK_TOP_MAINPLL_D3 124137#define CLK_TOP_MAINPLL_D4 125138#define CLK_TOP_MAINPLL_D4_D2 126139#define CLK_TOP_MAINPLL_D4_D4 127140#define CLK_TOP_MAINPLL_D4_D8 128141#define CLK_TOP_MAINPLL_D5 129142#define CLK_TOP_MAINPLL_D5_D2 130143#define CLK_TOP_MAINPLL_D5_D4 131144#define CLK_TOP_MAINPLL_D5_D8 132145#define CLK_TOP_MAINPLL_D6 133146#define CLK_TOP_MAINPLL_D6_D2 134147#define CLK_TOP_MAINPLL_D6_D4 135148#define CLK_TOP_MAINPLL_D6_D8 136149#define CLK_TOP_MAINPLL_D7 137150#define CLK_TOP_MAINPLL_D7_D2 138151#define CLK_TOP_MAINPLL_D7_D4 139152#define CLK_TOP_MAINPLL_D7_D8 140153#define CLK_TOP_MAINPLL_D9 141154#define CLK_TOP_UNIVPLL_D2 142155#define CLK_TOP_UNIVPLL_D3 143156#define CLK_TOP_UNIVPLL_D4 144157#define CLK_TOP_UNIVPLL_D4_D2 145158#define CLK_TOP_UNIVPLL_D4_D4 146159#define CLK_TOP_UNIVPLL_D4_D8 147160#define CLK_TOP_UNIVPLL_D5 148161#define CLK_TOP_UNIVPLL_D5_D2 149162#define CLK_TOP_UNIVPLL_D5_D4 150163#define CLK_TOP_UNIVPLL_D5_D8 151164#define CLK_TOP_UNIVPLL_D6 152165#define CLK_TOP_UNIVPLL_D6_D2 153166#define CLK_TOP_UNIVPLL_D6_D4 154167#define CLK_TOP_UNIVPLL_D6_D8 155168#define CLK_TOP_UNIVPLL_D6_D16 156169#define CLK_TOP_UNIVPLL_D7 157170#define CLK_TOP_UNIVPLL_192M 158171#define CLK_TOP_UNIVPLL_192M_D4 159172#define CLK_TOP_UNIVPLL_192M_D8 160173#define CLK_TOP_UNIVPLL_192M_D16 161174#define CLK_TOP_UNIVPLL_192M_D32 162175#define CLK_TOP_APLL1_D3 163176#define CLK_TOP_APLL1_D4 164177#define CLK_TOP_APLL2_D3 165178#define CLK_TOP_APLL2_D4 166179#define CLK_TOP_APLL3_D4 167180#define CLK_TOP_APLL4_D4 168181#define CLK_TOP_APLL5_D4 169182#define CLK_TOP_HDMIRX_APLL_D3 170183#define CLK_TOP_HDMIRX_APLL_D4 171184#define CLK_TOP_HDMIRX_APLL_D6 172185#define CLK_TOP_MMPLL_D4 173186#define CLK_TOP_MMPLL_D4_D2 174187#define CLK_TOP_MMPLL_D4_D4 175188#define CLK_TOP_MMPLL_D5 176189#define CLK_TOP_MMPLL_D5_D2 177190#define CLK_TOP_MMPLL_D5_D4 178191#define CLK_TOP_MMPLL_D6 179192#define CLK_TOP_MMPLL_D6_D2 180193#define CLK_TOP_MMPLL_D7 181194#define CLK_TOP_MMPLL_D9 182195#define CLK_TOP_TVDPLL1_D2 183196#define CLK_TOP_TVDPLL1_D4 184197#define CLK_TOP_TVDPLL1_D8 185198#define CLK_TOP_TVDPLL1_D16 186199#define CLK_TOP_TVDPLL2_D2 187200#define CLK_TOP_TVDPLL2_D4 188201#define CLK_TOP_TVDPLL2_D8 189202#define CLK_TOP_TVDPLL2_D16 190203#define CLK_TOP_MSDCPLL_D2 191204#define CLK_TOP_MSDCPLL_D4 192205#define CLK_TOP_MSDCPLL_D16 193206#define CLK_TOP_ETHPLL_D2 194207#define CLK_TOP_ETHPLL_D8 195208#define CLK_TOP_ETHPLL_D10 196209#define CLK_TOP_DGIPLL_D2 197210#define CLK_TOP_ULPOSC1 198211#define CLK_TOP_ULPOSC1_D2 199212#define CLK_TOP_ULPOSC1_D4 200213#define CLK_TOP_ULPOSC1_D7 201214#define CLK_TOP_ULPOSC1_D8 202215#define CLK_TOP_ULPOSC1_D10 203216#define CLK_TOP_ULPOSC1_D16 204217#define CLK_TOP_ULPOSC2 205218#define CLK_TOP_ADSPPLL_D2 206219#define CLK_TOP_ADSPPLL_D4 207220#define CLK_TOP_ADSPPLL_D8 208221#define CLK_TOP_MEM_466M 209222#define CLK_TOP_MPHONE_SLAVE_B 210223#define CLK_TOP_PEXTP_PIPE 211224#define CLK_TOP_UFS_RX_SYMBOL 212225#define CLK_TOP_UFS_TX_SYMBOL 213226#define CLK_TOP_SSUSB_U3PHY_P1_P_P0 214227#define CLK_TOP_UFS_RX_SYMBOL1 215228#define CLK_TOP_FPC 216229#define CLK_TOP_HDMIRX_P 217230#define CLK_TOP_APLL12_DIV0 218231#define CLK_TOP_APLL12_DIV1 219232#define CLK_TOP_APLL12_DIV2 220233#define CLK_TOP_APLL12_DIV3 221234#define CLK_TOP_APLL12_DIV4 222235#define CLK_TOP_APLL12_DIV9 223236#define CLK_TOP_CFG_VPP0 224237#define CLK_TOP_CFG_VPP1 225238#define CLK_TOP_CFG_VDO0 226239#define CLK_TOP_CFG_VDO1 227240#define CLK_TOP_CFG_UNIPLL_SES 228241#define CLK_TOP_CFG_26M_VPP0 229242#define CLK_TOP_CFG_26M_VPP1 230243#define CLK_TOP_CFG_26M_AUD 231244#define CLK_TOP_CFG_AXI_EAST 232245#define CLK_TOP_CFG_AXI_EAST_NORTH 233246#define CLK_TOP_CFG_AXI_NORTH 234247#define CLK_TOP_CFG_AXI_SOUTH 235248#define CLK_TOP_CFG_EXT_TEST 236249#define CLK_TOP_SSUSB_REF 237250#define CLK_TOP_SSUSB_PHY_REF 238251#define CLK_TOP_SSUSB_P1_REF 239252#define CLK_TOP_SSUSB_PHY_P1_REF 240253#define CLK_TOP_SSUSB_P2_REF 241254#define CLK_TOP_SSUSB_PHY_P2_REF 242255#define CLK_TOP_SSUSB_P3_REF 243256#define CLK_TOP_SSUSB_PHY_P3_REF 244257#define CLK_TOP_NR_CLK 245258 259/* INFRACFG_AO */260 261#define CLK_INFRA_AO_PMIC_TMR 0262#define CLK_INFRA_AO_PMIC_AP 1263#define CLK_INFRA_AO_PMIC_MD 2264#define CLK_INFRA_AO_PMIC_CONN 3265#define CLK_INFRA_AO_SEJ 4266#define CLK_INFRA_AO_APXGPT 5267#define CLK_INFRA_AO_GCE 6268#define CLK_INFRA_AO_GCE2 7269#define CLK_INFRA_AO_THERM 8270#define CLK_INFRA_AO_PWM_H 9271#define CLK_INFRA_AO_PWM1 10272#define CLK_INFRA_AO_PWM2 11273#define CLK_INFRA_AO_PWM3 12274#define CLK_INFRA_AO_PWM4 13275#define CLK_INFRA_AO_PWM 14276#define CLK_INFRA_AO_UART0 15277#define CLK_INFRA_AO_UART1 16278#define CLK_INFRA_AO_UART2 17279#define CLK_INFRA_AO_UART3 18280#define CLK_INFRA_AO_UART4 19281#define CLK_INFRA_AO_GCE_26M 20282#define CLK_INFRA_AO_CQ_DMA_FPC 21283#define CLK_INFRA_AO_UART5 22284#define CLK_INFRA_AO_HDMI_26M 23285#define CLK_INFRA_AO_SPI0 24286#define CLK_INFRA_AO_MSDC0 25287#define CLK_INFRA_AO_MSDC1 26288#define CLK_INFRA_AO_CG1_MSDC2 27289#define CLK_INFRA_AO_MSDC0_SRC 28290#define CLK_INFRA_AO_TRNG 29291#define CLK_INFRA_AO_AUXADC 30292#define CLK_INFRA_AO_CPUM 31293#define CLK_INFRA_AO_HDMI_32K 32294#define CLK_INFRA_AO_CEC_66M_H 33295#define CLK_INFRA_AO_IRRX 34296#define CLK_INFRA_AO_PCIE_TL_26M 35297#define CLK_INFRA_AO_MSDC1_SRC 36298#define CLK_INFRA_AO_CEC_66M_B 37299#define CLK_INFRA_AO_PCIE_TL_96M 38300#define CLK_INFRA_AO_DEVICE_APC 39301#define CLK_INFRA_AO_ECC_66M_H 40302#define CLK_INFRA_AO_DEBUGSYS 41303#define CLK_INFRA_AO_AUDIO 42304#define CLK_INFRA_AO_PCIE_TL_32K 43305#define CLK_INFRA_AO_DBG_TRACE 44306#define CLK_INFRA_AO_DRAMC_F26M 45307#define CLK_INFRA_AO_IRTX 46308#define CLK_INFRA_AO_SSUSB 47309#define CLK_INFRA_AO_DISP_PWM 48310#define CLK_INFRA_AO_CLDMA_B 49311#define CLK_INFRA_AO_AUDIO_26M_B 50312#define CLK_INFRA_AO_SPI1 51313#define CLK_INFRA_AO_SPI2 52314#define CLK_INFRA_AO_SPI3 53315#define CLK_INFRA_AO_UNIPRO_SYS 54316#define CLK_INFRA_AO_UNIPRO_TICK 55317#define CLK_INFRA_AO_UFS_MP_SAP_B 56318#define CLK_INFRA_AO_PWRMCU 57319#define CLK_INFRA_AO_PWRMCU_BUS_H 58320#define CLK_INFRA_AO_APDMA_B 59321#define CLK_INFRA_AO_SPI4 60322#define CLK_INFRA_AO_SPI5 61323#define CLK_INFRA_AO_CQ_DMA 62324#define CLK_INFRA_AO_AES_UFSFDE 63325#define CLK_INFRA_AO_AES 64326#define CLK_INFRA_AO_UFS_TICK 65327#define CLK_INFRA_AO_SSUSB_XHCI 66328#define CLK_INFRA_AO_MSDC0_SELF 67329#define CLK_INFRA_AO_MSDC1_SELF 68330#define CLK_INFRA_AO_MSDC2_SELF 69331#define CLK_INFRA_AO_I2S_DMA 70332#define CLK_INFRA_AO_AP_MSDC0 71333#define CLK_INFRA_AO_MD_MSDC0 72334#define CLK_INFRA_AO_CG3_MSDC2 73335#define CLK_INFRA_AO_GCPU 74336#define CLK_INFRA_AO_PCIE_PERI_26M 75337#define CLK_INFRA_AO_GCPU_66M_B 76338#define CLK_INFRA_AO_GCPU_133M_B 77339#define CLK_INFRA_AO_DISP_PWM1 78340#define CLK_INFRA_AO_FBIST2FPC 79341#define CLK_INFRA_AO_DEVICE_APC_SYNC 80342#define CLK_INFRA_AO_PCIE_P1_PERI_26M 81343#define CLK_INFRA_AO_SPIS0 82344#define CLK_INFRA_AO_SPIS1 83345#define CLK_INFRA_AO_133M_M_PERI 84346#define CLK_INFRA_AO_66M_M_PERI 85347#define CLK_INFRA_AO_PCIE_PL_P_250M_P0 86348#define CLK_INFRA_AO_PCIE_PL_P_250M_P1 87349#define CLK_INFRA_AO_PCIE_P1_TL_96M 88350#define CLK_INFRA_AO_AES_MSDCFDE_0P 89351#define CLK_INFRA_AO_UFS_TX_SYMBOL 90352#define CLK_INFRA_AO_UFS_RX_SYMBOL 91353#define CLK_INFRA_AO_UFS_RX_SYMBOL1 92354#define CLK_INFRA_AO_PERI_UFS_MEM_SUB 93355#define CLK_INFRA_AO_NR_CLK 94356 357/* APMIXEDSYS */358 359#define CLK_APMIXED_NNAPLL 0360#define CLK_APMIXED_RESPLL 1361#define CLK_APMIXED_ETHPLL 2362#define CLK_APMIXED_MSDCPLL 3363#define CLK_APMIXED_TVDPLL1 4364#define CLK_APMIXED_TVDPLL2 5365#define CLK_APMIXED_MMPLL 6366#define CLK_APMIXED_MAINPLL 7367#define CLK_APMIXED_VDECPLL 8368#define CLK_APMIXED_IMGPLL 9369#define CLK_APMIXED_UNIVPLL 10370#define CLK_APMIXED_HDMIPLL1 11371#define CLK_APMIXED_HDMIPLL2 12372#define CLK_APMIXED_HDMIRX_APLL 13373#define CLK_APMIXED_USB1PLL 14374#define CLK_APMIXED_ADSPPLL 15375#define CLK_APMIXED_APLL1 16376#define CLK_APMIXED_APLL2 17377#define CLK_APMIXED_APLL3 18378#define CLK_APMIXED_APLL4 19379#define CLK_APMIXED_APLL5 20380#define CLK_APMIXED_MFGPLL 21381#define CLK_APMIXED_DGIPLL 22382#define CLK_APMIXED_PLL_SSUSB26M 23383#define CLK_APMIXED_NR_CLK 24384 385/* SCP_ADSP */386 387#define CLK_SCP_ADSP_AUDIODSP 0388#define CLK_SCP_ADSP_NR_CLK 1389 390/* PERICFG_AO */391 392#define CLK_PERI_AO_ETHERNET 0393#define CLK_PERI_AO_ETHERNET_BUS 1394#define CLK_PERI_AO_FLASHIF_BUS 2395#define CLK_PERI_AO_FLASHIF_FLASH 3396#define CLK_PERI_AO_SSUSB_1P_BUS 4397#define CLK_PERI_AO_SSUSB_1P_XHCI 5398#define CLK_PERI_AO_SSUSB_2P_BUS 6399#define CLK_PERI_AO_SSUSB_2P_XHCI 7400#define CLK_PERI_AO_SSUSB_3P_BUS 8401#define CLK_PERI_AO_SSUSB_3P_XHCI 9402#define CLK_PERI_AO_SPINFI 10403#define CLK_PERI_AO_ETHERNET_MAC 11404#define CLK_PERI_AO_NFI_H 12405#define CLK_PERI_AO_FNFI1X 13406#define CLK_PERI_AO_PCIE_P0_MEM 14407#define CLK_PERI_AO_PCIE_P1_MEM 15408#define CLK_PERI_AO_NR_CLK 16409 410/* IMP_IIC_WRAP_S */411 412#define CLK_IMP_IIC_WRAP_S_I2C5 0413#define CLK_IMP_IIC_WRAP_S_I2C6 1414#define CLK_IMP_IIC_WRAP_S_I2C7 2415#define CLK_IMP_IIC_WRAP_S_NR_CLK 3416 417/* IMP_IIC_WRAP_W */418 419#define CLK_IMP_IIC_WRAP_W_I2C0 0420#define CLK_IMP_IIC_WRAP_W_I2C1 1421#define CLK_IMP_IIC_WRAP_W_I2C2 2422#define CLK_IMP_IIC_WRAP_W_I2C3 3423#define CLK_IMP_IIC_WRAP_W_I2C4 4424#define CLK_IMP_IIC_WRAP_W_NR_CLK 5425 426/* MFGCFG */427 428#define CLK_MFG_BG3D 0429#define CLK_MFG_NR_CLK 1430 431/* VPPSYS0 */432 433#define CLK_VPP0_MDP_FG 0434#define CLK_VPP0_STITCH 1435#define CLK_VPP0_PADDING 2436#define CLK_VPP0_MDP_TCC 3437#define CLK_VPP0_WARP0_ASYNC_TX 4438#define CLK_VPP0_WARP1_ASYNC_TX 5439#define CLK_VPP0_MUTEX 6440#define CLK_VPP0_VPP02VPP1_RELAY 7441#define CLK_VPP0_VPP12VPP0_ASYNC 8442#define CLK_VPP0_MMSYSRAM_TOP 9443#define CLK_VPP0_MDP_AAL 10444#define CLK_VPP0_MDP_RSZ 11445#define CLK_VPP0_SMI_COMMON 12446#define CLK_VPP0_GALS_VDO0_LARB0 13447#define CLK_VPP0_GALS_VDO0_LARB1 14448#define CLK_VPP0_GALS_VENCSYS 15449#define CLK_VPP0_GALS_VENCSYS_CORE1 16450#define CLK_VPP0_GALS_INFRA 17451#define CLK_VPP0_GALS_CAMSYS 18452#define CLK_VPP0_GALS_VPP1_LARB5 19453#define CLK_VPP0_GALS_VPP1_LARB6 20454#define CLK_VPP0_SMI_REORDER 21455#define CLK_VPP0_SMI_IOMMU 22456#define CLK_VPP0_GALS_IMGSYS_CAMSYS 23457#define CLK_VPP0_MDP_RDMA 24458#define CLK_VPP0_MDP_WROT 25459#define CLK_VPP0_GALS_EMI0_EMI1 26460#define CLK_VPP0_SMI_SUB_COMMON_REORDER 27461#define CLK_VPP0_SMI_RSI 28462#define CLK_VPP0_SMI_COMMON_LARB4 29463#define CLK_VPP0_GALS_VDEC_VDEC_CORE1 30464#define CLK_VPP0_GALS_VPP1_WPE 31465#define CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1 32466#define CLK_VPP0_FAKE_ENG 33467#define CLK_VPP0_MDP_HDR 34468#define CLK_VPP0_MDP_TDSHP 35469#define CLK_VPP0_MDP_COLOR 36470#define CLK_VPP0_MDP_OVL 37471#define CLK_VPP0_WARP0_RELAY 38472#define CLK_VPP0_WARP0_MDP_DL_ASYNC 39473#define CLK_VPP0_WARP1_RELAY 40474#define CLK_VPP0_WARP1_MDP_DL_ASYNC 41475#define CLK_VPP0_NR_CLK 42476 477/* WPESYS */478 479#define CLK_WPE_VPP0 0480#define CLK_WPE_VPP1 1481#define CLK_WPE_SMI_LARB7 2482#define CLK_WPE_SMI_LARB8 3483#define CLK_WPE_EVENT_TX 4484#define CLK_WPE_SMI_LARB7_P 5485#define CLK_WPE_SMI_LARB8_P 6486#define CLK_WPE_NR_CLK 7487 488/* WPESYS_VPP0 */489 490#define CLK_WPE_VPP0_VECI 0491#define CLK_WPE_VPP0_VEC2I 1492#define CLK_WPE_VPP0_VEC3I 2493#define CLK_WPE_VPP0_WPEO 3494#define CLK_WPE_VPP0_MSKO 4495#define CLK_WPE_VPP0_VGEN 5496#define CLK_WPE_VPP0_EXT 6497#define CLK_WPE_VPP0_VFC 7498#define CLK_WPE_VPP0_CACH0_TOP 8499#define CLK_WPE_VPP0_CACH0_DMA 9500#define CLK_WPE_VPP0_CACH1_TOP 10501#define CLK_WPE_VPP0_CACH1_DMA 11502#define CLK_WPE_VPP0_CACH2_TOP 12503#define CLK_WPE_VPP0_CACH2_DMA 13504#define CLK_WPE_VPP0_CACH3_TOP 14505#define CLK_WPE_VPP0_CACH3_DMA 15506#define CLK_WPE_VPP0_PSP 16507#define CLK_WPE_VPP0_PSP2 17508#define CLK_WPE_VPP0_SYNC 18509#define CLK_WPE_VPP0_C24 19510#define CLK_WPE_VPP0_MDP_CROP 20511#define CLK_WPE_VPP0_ISP_CROP 21512#define CLK_WPE_VPP0_TOP 22513#define CLK_WPE_VPP0_NR_CLK 23514 515/* WPESYS_VPP1 */516 517#define CLK_WPE_VPP1_VECI 0518#define CLK_WPE_VPP1_VEC2I 1519#define CLK_WPE_VPP1_VEC3I 2520#define CLK_WPE_VPP1_WPEO 3521#define CLK_WPE_VPP1_MSKO 4522#define CLK_WPE_VPP1_VGEN 5523#define CLK_WPE_VPP1_EXT 6524#define CLK_WPE_VPP1_VFC 7525#define CLK_WPE_VPP1_CACH0_TOP 8526#define CLK_WPE_VPP1_CACH0_DMA 9527#define CLK_WPE_VPP1_CACH1_TOP 10528#define CLK_WPE_VPP1_CACH1_DMA 11529#define CLK_WPE_VPP1_CACH2_TOP 12530#define CLK_WPE_VPP1_CACH2_DMA 13531#define CLK_WPE_VPP1_CACH3_TOP 14532#define CLK_WPE_VPP1_CACH3_DMA 15533#define CLK_WPE_VPP1_PSP 16534#define CLK_WPE_VPP1_PSP2 17535#define CLK_WPE_VPP1_SYNC 18536#define CLK_WPE_VPP1_C24 19537#define CLK_WPE_VPP1_MDP_CROP 20538#define CLK_WPE_VPP1_ISP_CROP 21539#define CLK_WPE_VPP1_TOP 22540#define CLK_WPE_VPP1_NR_CLK 23541 542/* VPPSYS1 */543 544#define CLK_VPP1_SVPP1_MDP_OVL 0545#define CLK_VPP1_SVPP1_MDP_TCC 1546#define CLK_VPP1_SVPP1_MDP_WROT 2547#define CLK_VPP1_SVPP1_VPP_PAD 3548#define CLK_VPP1_SVPP2_MDP_WROT 4549#define CLK_VPP1_SVPP2_VPP_PAD 5550#define CLK_VPP1_SVPP3_MDP_WROT 6551#define CLK_VPP1_SVPP3_VPP_PAD 7552#define CLK_VPP1_SVPP1_MDP_RDMA 8553#define CLK_VPP1_SVPP1_MDP_FG 9554#define CLK_VPP1_SVPP2_MDP_RDMA 10555#define CLK_VPP1_SVPP2_MDP_FG 11556#define CLK_VPP1_SVPP3_MDP_RDMA 12557#define CLK_VPP1_SVPP3_MDP_FG 13558#define CLK_VPP1_VPP_SPLIT 14559#define CLK_VPP1_SVPP2_VDO0_DL_RELAY 15560#define CLK_VPP1_SVPP1_MDP_TDSHP 16561#define CLK_VPP1_SVPP1_MDP_COLOR 17562#define CLK_VPP1_SVPP3_VDO1_DL_RELAY 18563#define CLK_VPP1_SVPP2_VPP_MERGE 19564#define CLK_VPP1_SVPP2_MDP_COLOR 20565#define CLK_VPP1_VPPSYS1_GALS 21566#define CLK_VPP1_SVPP3_VPP_MERGE 22567#define CLK_VPP1_SVPP3_MDP_COLOR 23568#define CLK_VPP1_VPPSYS1_LARB 24569#define CLK_VPP1_SVPP1_MDP_RSZ 25570#define CLK_VPP1_SVPP1_MDP_HDR 26571#define CLK_VPP1_SVPP1_MDP_AAL 27572#define CLK_VPP1_SVPP2_MDP_HDR 28573#define CLK_VPP1_SVPP2_MDP_AAL 29574#define CLK_VPP1_DL_ASYNC 30575#define CLK_VPP1_LARB5_FAKE_ENG 31576#define CLK_VPP1_SVPP3_MDP_HDR 32577#define CLK_VPP1_SVPP3_MDP_AAL 33578#define CLK_VPP1_SVPP2_VDO1_DL_RELAY 34579#define CLK_VPP1_LARB6_FAKE_ENG 35580#define CLK_VPP1_SVPP2_MDP_RSZ 36581#define CLK_VPP1_SVPP3_MDP_RSZ 37582#define CLK_VPP1_SVPP3_VDO0_DL_RELAY 38583#define CLK_VPP1_DISP_MUTEX 39584#define CLK_VPP1_SVPP2_MDP_TDSHP 40585#define CLK_VPP1_SVPP3_MDP_TDSHP 41586#define CLK_VPP1_VPP0_DL1_RELAY 42587#define CLK_VPP1_HDMI_META 43588#define CLK_VPP1_VPP_SPLIT_HDMI 44589#define CLK_VPP1_DGI_IN 45590#define CLK_VPP1_DGI_OUT 46591#define CLK_VPP1_VPP_SPLIT_DGI 47592#define CLK_VPP1_VPP0_DL_ASYNC 48593#define CLK_VPP1_VPP0_DL_RELAY 49594#define CLK_VPP1_VPP_SPLIT_26M 50595#define CLK_VPP1_NR_CLK 51596 597/* IMGSYS */598 599#define CLK_IMG_LARB9 0600#define CLK_IMG_TRAW0 1601#define CLK_IMG_TRAW1 2602#define CLK_IMG_TRAW2 3603#define CLK_IMG_TRAW3 4604#define CLK_IMG_DIP0 5605#define CLK_IMG_WPE0 6606#define CLK_IMG_IPE 7607#define CLK_IMG_DIP1 8608#define CLK_IMG_WPE1 9609#define CLK_IMG_GALS 10610#define CLK_IMG_NR_CLK 11611 612/* IMGSYS1_DIP_TOP */613 614#define CLK_IMG1_DIP_TOP_LARB10 0615#define CLK_IMG1_DIP_TOP_DIP_TOP 1616#define CLK_IMG1_DIP_TOP_NR_CLK 2617 618/* IMGSYS1_DIP_NR */619 620#define CLK_IMG1_DIP_NR_RESERVE 0621#define CLK_IMG1_DIP_NR_DIP_NR 1622#define CLK_IMG1_DIP_NR_NR_CLK 2623 624/* IMGSYS1_WPE */625 626#define CLK_IMG1_WPE_LARB11 0627#define CLK_IMG1_WPE_WPE 1628#define CLK_IMG1_WPE_NR_CLK 2629 630/* IPESYS */631 632#define CLK_IPE_DPE 0633#define CLK_IPE_FDVT 1634#define CLK_IPE_ME 2635#define CLK_IPE_TOP 3636#define CLK_IPE_SMI_LARB12 4637#define CLK_IPE_NR_CLK 5638 639/* CAMSYS */640 641#define CLK_CAM_LARB13 0642#define CLK_CAM_LARB14 1643#define CLK_CAM_MAIN_CAM 2644#define CLK_CAM_MAIN_CAMTG 3645#define CLK_CAM_SENINF 4646#define CLK_CAM_GCAMSVA 5647#define CLK_CAM_GCAMSVB 6648#define CLK_CAM_GCAMSVC 7649#define CLK_CAM_SCAMSA 8650#define CLK_CAM_SCAMSB 9651#define CLK_CAM_CAMSV_TOP 10652#define CLK_CAM_CAMSV_CQ 11653#define CLK_CAM_ADL 12654#define CLK_CAM_ASG 13655#define CLK_CAM_PDA 14656#define CLK_CAM_FAKE_ENG 15657#define CLK_CAM_MAIN_MRAW0 16658#define CLK_CAM_MAIN_MRAW1 17659#define CLK_CAM_MAIN_MRAW2 18660#define CLK_CAM_MAIN_MRAW3 19661#define CLK_CAM_CAM2MM0_GALS 20662#define CLK_CAM_CAM2MM1_GALS 21663#define CLK_CAM_CAM2SYS_GALS 22664#define CLK_CAM_NR_CLK 23665 666/* CAMSYS_RAWA */667 668#define CLK_CAM_RAWA_LARBX 0669#define CLK_CAM_RAWA_CAM 1670#define CLK_CAM_RAWA_CAMTG 2671#define CLK_CAM_RAWA_NR_CLK 3672 673/* CAMSYS_YUVA */674 675#define CLK_CAM_YUVA_LARBX 0676#define CLK_CAM_YUVA_CAM 1677#define CLK_CAM_YUVA_CAMTG 2678#define CLK_CAM_YUVA_NR_CLK 3679 680/* CAMSYS_RAWB */681 682#define CLK_CAM_RAWB_LARBX 0683#define CLK_CAM_RAWB_CAM 1684#define CLK_CAM_RAWB_CAMTG 2685#define CLK_CAM_RAWB_NR_CLK 3686 687/* CAMSYS_YUVB */688 689#define CLK_CAM_YUVB_LARBX 0690#define CLK_CAM_YUVB_CAM 1691#define CLK_CAM_YUVB_CAMTG 2692#define CLK_CAM_YUVB_NR_CLK 3693 694/* CAMSYS_MRAW */695 696#define CLK_CAM_MRAW_LARBX 0697#define CLK_CAM_MRAW_CAMTG 1698#define CLK_CAM_MRAW_MRAW0 2699#define CLK_CAM_MRAW_MRAW1 3700#define CLK_CAM_MRAW_MRAW2 4701#define CLK_CAM_MRAW_MRAW3 5702#define CLK_CAM_MRAW_NR_CLK 6703 704/* CCUSYS */705 706#define CLK_CCU_LARB18 0707#define CLK_CCU_AHB 1708#define CLK_CCU_CCU0 2709#define CLK_CCU_CCU1 3710#define CLK_CCU_NR_CLK 4711 712/* VDECSYS_SOC */713 714#define CLK_VDEC_SOC_LARB1 0715#define CLK_VDEC_SOC_LAT 1716#define CLK_VDEC_SOC_VDEC 2717#define CLK_VDEC_SOC_NR_CLK 3718 719/* VDECSYS */720 721#define CLK_VDEC_LARB1 0722#define CLK_VDEC_LAT 1723#define CLK_VDEC_VDEC 2724#define CLK_VDEC_NR_CLK 3725 726/* VDECSYS_CORE1 */727 728#define CLK_VDEC_CORE1_LARB1 0729#define CLK_VDEC_CORE1_LAT 1730#define CLK_VDEC_CORE1_VDEC 2731#define CLK_VDEC_CORE1_NR_CLK 3732 733/* APUSYS_PLL */734 735#define CLK_APUSYS_PLL_APUPLL 0736#define CLK_APUSYS_PLL_NPUPLL 1737#define CLK_APUSYS_PLL_APUPLL1 2738#define CLK_APUSYS_PLL_APUPLL2 3739#define CLK_APUSYS_PLL_NR_CLK 4740 741/* VENCSYS */742 743#define CLK_VENC_LARB 0744#define CLK_VENC_VENC 1745#define CLK_VENC_JPGENC 2746#define CLK_VENC_JPGDEC 3747#define CLK_VENC_JPGDEC_C1 4748#define CLK_VENC_GALS 5749#define CLK_VENC_NR_CLK 6750 751/* VENCSYS_CORE1 */752 753#define CLK_VENC_CORE1_LARB 0754#define CLK_VENC_CORE1_VENC 1755#define CLK_VENC_CORE1_JPGENC 2756#define CLK_VENC_CORE1_JPGDEC 3757#define CLK_VENC_CORE1_JPGDEC_C1 4758#define CLK_VENC_CORE1_GALS 5759#define CLK_VENC_CORE1_NR_CLK 6760 761/* VDOSYS0 */762 763#define CLK_VDO0_DISP_OVL0 0764#define CLK_VDO0_DISP_COLOR0 1765#define CLK_VDO0_DISP_COLOR1 2766#define CLK_VDO0_DISP_CCORR0 3767#define CLK_VDO0_DISP_CCORR1 4768#define CLK_VDO0_DISP_AAL0 5769#define CLK_VDO0_DISP_AAL1 6770#define CLK_VDO0_DISP_GAMMA0 7771#define CLK_VDO0_DISP_GAMMA1 8772#define CLK_VDO0_DISP_DITHER0 9773#define CLK_VDO0_DISP_DITHER1 10774#define CLK_VDO0_DISP_OVL1 11775#define CLK_VDO0_DISP_WDMA0 12776#define CLK_VDO0_DISP_WDMA1 13777#define CLK_VDO0_DISP_RDMA0 14778#define CLK_VDO0_DISP_RDMA1 15779#define CLK_VDO0_DSI0 16780#define CLK_VDO0_DSI1 17781#define CLK_VDO0_DSC_WRAP0 18782#define CLK_VDO0_VPP_MERGE0 19783#define CLK_VDO0_DP_INTF0 20784#define CLK_VDO0_DISP_MUTEX0 21785#define CLK_VDO0_DISP_IL_ROT0 22786#define CLK_VDO0_APB_BUS 23787#define CLK_VDO0_FAKE_ENG0 24788#define CLK_VDO0_FAKE_ENG1 25789#define CLK_VDO0_DL_ASYNC0 26790#define CLK_VDO0_DL_ASYNC1 27791#define CLK_VDO0_DL_ASYNC2 28792#define CLK_VDO0_DL_ASYNC3 29793#define CLK_VDO0_DL_ASYNC4 30794#define CLK_VDO0_DISP_MONITOR0 31795#define CLK_VDO0_DISP_MONITOR1 32796#define CLK_VDO0_DISP_MONITOR2 33797#define CLK_VDO0_DISP_MONITOR3 34798#define CLK_VDO0_DISP_MONITOR4 35799#define CLK_VDO0_SMI_GALS 36800#define CLK_VDO0_SMI_COMMON 37801#define CLK_VDO0_SMI_EMI 38802#define CLK_VDO0_SMI_IOMMU 39803#define CLK_VDO0_SMI_LARB 40804#define CLK_VDO0_SMI_RSI 41805#define CLK_VDO0_DSI0_DSI 42806#define CLK_VDO0_DSI1_DSI 43807#define CLK_VDO0_DP_INTF0_DP_INTF 44808#define CLK_VDO0_NR_CLK 45809 810/* VDOSYS1 */811 812#define CLK_VDO1_SMI_LARB2 0813#define CLK_VDO1_SMI_LARB3 1814#define CLK_VDO1_GALS 2815#define CLK_VDO1_FAKE_ENG0 3816#define CLK_VDO1_FAKE_ENG 4817#define CLK_VDO1_MDP_RDMA0 5818#define CLK_VDO1_MDP_RDMA1 6819#define CLK_VDO1_MDP_RDMA2 7820#define CLK_VDO1_MDP_RDMA3 8821#define CLK_VDO1_VPP_MERGE0 9822#define CLK_VDO1_VPP_MERGE1 10823#define CLK_VDO1_VPP_MERGE2 11824#define CLK_VDO1_VPP_MERGE3 12825#define CLK_VDO1_VPP_MERGE4 13826#define CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC 14827#define CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC 15828#define CLK_VDO1_DISP_MUTEX 16829#define CLK_VDO1_MDP_RDMA4 17830#define CLK_VDO1_MDP_RDMA5 18831#define CLK_VDO1_MDP_RDMA6 19832#define CLK_VDO1_MDP_RDMA7 20833#define CLK_VDO1_DP_INTF0_MM 21834#define CLK_VDO1_DPI0_MM 22835#define CLK_VDO1_DPI1_MM 23836#define CLK_VDO1_DISP_MONITOR 24837#define CLK_VDO1_MERGE0_DL_ASYNC 25838#define CLK_VDO1_MERGE1_DL_ASYNC 26839#define CLK_VDO1_MERGE2_DL_ASYNC 27840#define CLK_VDO1_MERGE3_DL_ASYNC 28841#define CLK_VDO1_MERGE4_DL_ASYNC 29842#define CLK_VDO1_VDO0_DSC_TO_VDO1_DL_ASYNC 30843#define CLK_VDO1_VDO0_MERGE_TO_VDO1_DL_ASYNC 31844#define CLK_VDO1_HDR_VDO_FE0 32845#define CLK_VDO1_HDR_GFX_FE0 33846#define CLK_VDO1_HDR_VDO_BE 34847#define CLK_VDO1_HDR_VDO_FE1 35848#define CLK_VDO1_HDR_GFX_FE1 36849#define CLK_VDO1_DISP_MIXER 37850#define CLK_VDO1_HDR_VDO_FE0_DL_ASYNC 38851#define CLK_VDO1_HDR_VDO_FE1_DL_ASYNC 39852#define CLK_VDO1_HDR_GFX_FE0_DL_ASYNC 40853#define CLK_VDO1_HDR_GFX_FE1_DL_ASYNC 41854#define CLK_VDO1_HDR_VDO_BE_DL_ASYNC 42855#define CLK_VDO1_DPI0 43856#define CLK_VDO1_DISP_MONITOR_DPI0 44857#define CLK_VDO1_DPI1 45858#define CLK_VDO1_DISP_MONITOR_DPI1 46859#define CLK_VDO1_DPINTF 47860#define CLK_VDO1_DISP_MONITOR_DPINTF 48861#define CLK_VDO1_26M_SLOW 49862#define CLK_VDO1_DPI1_HDMI 50863#define CLK_VDO1_NR_CLK 51864 865 866#endif /* _DT_BINDINGS_CLK_MT8195_H */867