229 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2019 MediaTek Inc.4 * Copyright (c) 2019 BayLibre, SAS.5 * Author: James Liao <jamesjj.liao@mediatek.com>6 */7 8#ifndef _DT_BINDINGS_CLK_MT8516_H9#define _DT_BINDINGS_CLK_MT8516_H10 11/* APMIXEDSYS */12 13#define CLK_APMIXED_ARMPLL 014#define CLK_APMIXED_MAINPLL 115#define CLK_APMIXED_UNIVPLL 216#define CLK_APMIXED_MMPLL 317#define CLK_APMIXED_APLL1 418#define CLK_APMIXED_APLL2 519#define CLK_APMIXED_NR_CLK 620 21/* INFRACFG */22 23#define CLK_IFR_MUX1_SEL 024#define CLK_IFR_ETH_25M_SEL 125#define CLK_IFR_I2C0_SEL 226#define CLK_IFR_I2C1_SEL 327#define CLK_IFR_I2C2_SEL 428#define CLK_IFR_NR_CLK 529 30/* TOPCKGEN */31 32#define CLK_TOP_CLK_NULL 033#define CLK_TOP_I2S_INFRA_BCK 134#define CLK_TOP_MEMPLL 235#define CLK_TOP_DMPLL 336#define CLK_TOP_MAINPLL_D2 437#define CLK_TOP_MAINPLL_D4 538#define CLK_TOP_MAINPLL_D8 639#define CLK_TOP_MAINPLL_D16 740#define CLK_TOP_MAINPLL_D11 841#define CLK_TOP_MAINPLL_D22 942#define CLK_TOP_MAINPLL_D3 1043#define CLK_TOP_MAINPLL_D6 1144#define CLK_TOP_MAINPLL_D12 1245#define CLK_TOP_MAINPLL_D5 1346#define CLK_TOP_MAINPLL_D10 1447#define CLK_TOP_MAINPLL_D20 1548#define CLK_TOP_MAINPLL_D40 1649#define CLK_TOP_MAINPLL_D7 1750#define CLK_TOP_MAINPLL_D14 1851#define CLK_TOP_UNIVPLL_D2 1952#define CLK_TOP_UNIVPLL_D4 2053#define CLK_TOP_UNIVPLL_D8 2154#define CLK_TOP_UNIVPLL_D16 2255#define CLK_TOP_UNIVPLL_D3 2356#define CLK_TOP_UNIVPLL_D6 2457#define CLK_TOP_UNIVPLL_D12 2558#define CLK_TOP_UNIVPLL_D24 2659#define CLK_TOP_UNIVPLL_D5 2760#define CLK_TOP_UNIVPLL_D20 2861#define CLK_TOP_MMPLL380M 2962#define CLK_TOP_MMPLL_D2 3063#define CLK_TOP_MMPLL_200M 3164#define CLK_TOP_USB_PHY48M 3265#define CLK_TOP_APLL1 3366#define CLK_TOP_APLL1_D2 3467#define CLK_TOP_APLL1_D4 3568#define CLK_TOP_APLL1_D8 3669#define CLK_TOP_APLL2 3770#define CLK_TOP_APLL2_D2 3871#define CLK_TOP_APLL2_D4 3972#define CLK_TOP_APLL2_D8 4073#define CLK_TOP_CLK26M 4174#define CLK_TOP_CLK26M_D2 4275#define CLK_TOP_AHB_INFRA_D2 4376#define CLK_TOP_NFI1X 4477#define CLK_TOP_ETH_D2 4578#define CLK_TOP_THEM 4679#define CLK_TOP_APDMA 4780#define CLK_TOP_I2C0 4881#define CLK_TOP_I2C1 4982#define CLK_TOP_AUXADC1 5083#define CLK_TOP_NFI 5184#define CLK_TOP_NFIECC 5285#define CLK_TOP_DEBUGSYS 5386#define CLK_TOP_PWM 5487#define CLK_TOP_UART0 5588#define CLK_TOP_UART1 5689#define CLK_TOP_BTIF 5790#define CLK_TOP_USB 5891#define CLK_TOP_FLASHIF_26M 5992#define CLK_TOP_AUXADC2 6093#define CLK_TOP_I2C2 6194#define CLK_TOP_MSDC0 6295#define CLK_TOP_MSDC1 6396#define CLK_TOP_NFI2X 6497#define CLK_TOP_PMICWRAP_AP 6598#define CLK_TOP_SEJ 6699#define CLK_TOP_MEMSLP_DLYER 67100#define CLK_TOP_SPI 68101#define CLK_TOP_APXGPT 69102#define CLK_TOP_AUDIO 70103#define CLK_TOP_PMICWRAP_MD 71104#define CLK_TOP_PMICWRAP_CONN 72105#define CLK_TOP_PMICWRAP_26M 73106#define CLK_TOP_AUX_ADC 74107#define CLK_TOP_AUX_TP 75108#define CLK_TOP_MSDC2 76109#define CLK_TOP_RBIST 77110#define CLK_TOP_NFI_BUS 78111#define CLK_TOP_GCE 79112#define CLK_TOP_TRNG 80113#define CLK_TOP_SEJ_13M 81114#define CLK_TOP_AES 82115#define CLK_TOP_PWM_B 83116#define CLK_TOP_PWM1_FB 84117#define CLK_TOP_PWM2_FB 85118#define CLK_TOP_PWM3_FB 86119#define CLK_TOP_PWM4_FB 87120#define CLK_TOP_PWM5_FB 88121#define CLK_TOP_USB_1P 89122#define CLK_TOP_FLASHIF_FREERUN 90123#define CLK_TOP_66M_ETH 91124#define CLK_TOP_133M_ETH 92125#define CLK_TOP_FETH_25M 93126#define CLK_TOP_FETH_50M 94127#define CLK_TOP_FLASHIF_AXI 95128#define CLK_TOP_USBIF 96129#define CLK_TOP_UART2 97130#define CLK_TOP_BSI 98131#define CLK_TOP_RG_SPINOR 99132#define CLK_TOP_RG_MSDC2 100133#define CLK_TOP_RG_ETH 101134#define CLK_TOP_RG_AUD1 102135#define CLK_TOP_RG_AUD2 103136#define CLK_TOP_RG_AUD_ENGEN1 104137#define CLK_TOP_RG_AUD_ENGEN2 105138#define CLK_TOP_RG_I2C 106139#define CLK_TOP_RG_PWM_INFRA 107140#define CLK_TOP_RG_AUD_SPDIF_IN 108141#define CLK_TOP_RG_UART2 109142#define CLK_TOP_RG_BSI 110143#define CLK_TOP_RG_DBG_ATCLK 111144#define CLK_TOP_RG_NFIECC 112145#define CLK_TOP_RG_APLL1_D2_EN 113146#define CLK_TOP_RG_APLL1_D4_EN 114147#define CLK_TOP_RG_APLL1_D8_EN 115148#define CLK_TOP_RG_APLL2_D2_EN 116149#define CLK_TOP_RG_APLL2_D4_EN 117150#define CLK_TOP_RG_APLL2_D8_EN 118151#define CLK_TOP_APLL12_DIV0 119152#define CLK_TOP_APLL12_DIV1 120153#define CLK_TOP_APLL12_DIV2 121154#define CLK_TOP_APLL12_DIV3 122155#define CLK_TOP_APLL12_DIV4 123156#define CLK_TOP_APLL12_DIV4B 124157#define CLK_TOP_APLL12_DIV5 125158#define CLK_TOP_APLL12_DIV5B 126159#define CLK_TOP_APLL12_DIV6 127160#define CLK_TOP_UART0_SEL 128161#define CLK_TOP_EMI_DDRPHY_SEL 129162#define CLK_TOP_AHB_INFRA_SEL 130163#define CLK_TOP_MSDC0_SEL 131164#define CLK_TOP_UART1_SEL 132165#define CLK_TOP_MSDC1_SEL 133166#define CLK_TOP_PMICSPI_SEL 134167#define CLK_TOP_QAXI_AUD26M_SEL 135168#define CLK_TOP_AUD_INTBUS_SEL 136169#define CLK_TOP_NFI2X_PAD_SEL 137170#define CLK_TOP_NFI1X_PAD_SEL 138171#define CLK_TOP_DDRPHYCFG_SEL 139172#define CLK_TOP_USB_78M_SEL 140173#define CLK_TOP_SPINOR_SEL 141174#define CLK_TOP_MSDC2_SEL 142175#define CLK_TOP_ETH_SEL 143176#define CLK_TOP_AUD1_SEL 144177#define CLK_TOP_AUD2_SEL 145178#define CLK_TOP_AUD_ENGEN1_SEL 146179#define CLK_TOP_AUD_ENGEN2_SEL 147180#define CLK_TOP_I2C_SEL 148181#define CLK_TOP_AUD_I2S0_M_SEL 149182#define CLK_TOP_AUD_I2S1_M_SEL 150183#define CLK_TOP_AUD_I2S2_M_SEL 151184#define CLK_TOP_AUD_I2S3_M_SEL 152185#define CLK_TOP_AUD_I2S4_M_SEL 153186#define CLK_TOP_AUD_I2S5_M_SEL 154187#define CLK_TOP_AUD_SPDIF_B_SEL 155188#define CLK_TOP_PWM_SEL 156189#define CLK_TOP_SPI_SEL 157190#define CLK_TOP_AUD_SPDIFIN_SEL 158191#define CLK_TOP_UART2_SEL 159192#define CLK_TOP_BSI_SEL 160193#define CLK_TOP_DBG_ATCLK_SEL 161194#define CLK_TOP_CSW_NFIECC_SEL 162195#define CLK_TOP_NFIECC_SEL 163196#define CLK_TOP_APLL12_CK_DIV0 164197#define CLK_TOP_APLL12_CK_DIV1 165198#define CLK_TOP_APLL12_CK_DIV2 166199#define CLK_TOP_APLL12_CK_DIV3 167200#define CLK_TOP_APLL12_CK_DIV4 168201#define CLK_TOP_APLL12_CK_DIV4B 169202#define CLK_TOP_APLL12_CK_DIV5 170203#define CLK_TOP_APLL12_CK_DIV5B 171204#define CLK_TOP_APLL12_CK_DIV6 172205#define CLK_TOP_USB_78M 173206#define CLK_TOP_MSDC0_INFRA 174207#define CLK_TOP_MSDC1_INFRA 175208#define CLK_TOP_MSDC2_INFRA 176209#define CLK_TOP_NR_CLK 177210 211/* AUDSYS */212 213#define CLK_AUD_AFE 0214#define CLK_AUD_I2S 1215#define CLK_AUD_22M 2216#define CLK_AUD_24M 3217#define CLK_AUD_INTDIR 4218#define CLK_AUD_APLL2_TUNER 5219#define CLK_AUD_APLL_TUNER 6220#define CLK_AUD_HDMI 7221#define CLK_AUD_SPDF 8222#define CLK_AUD_ADC 9223#define CLK_AUD_DAC 10224#define CLK_AUD_DAC_PREDIS 11225#define CLK_AUD_TML 12226#define CLK_AUD_NR_CLK 13227 228#endif /* _DT_BINDINGS_CLK_MT8516_H */229