254 lines · c
1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */2/*3 * Copyright (C) 2023 Nuvoton Technologies.4 */5 6#ifndef __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H7#define __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H8 9/* external and internal oscillator clocks */10#define HXT 011#define HXT_GATE 112#define LXT 213#define LXT_GATE 314#define HIRC 415#define HIRC_GATE 516#define LIRC 617#define LIRC_GATE 718/* PLLs */19#define CAPLL 820#define SYSPLL 921#define DDRPLL 1022#define APLL 1123#define EPLL 1224#define VPLL 1325/* EPLL divider */26#define EPLL_DIV2 1427#define EPLL_DIV4 1528#define EPLL_DIV8 1629/* CPU clock, system clock, AXI, HCLK and PCLK */30#define CA35CLK_MUX 1731#define AXICLK_DIV2 1832#define AXICLK_DIV4 1933#define AXICLK_MUX 2034#define SYSCLK0_MUX 2135#define SYSCLK1_MUX 2236#define SYSCLK1_DIV2 2337#define HCLK0 2438#define HCLK1 2539#define HCLK2 2640#define PCLK0 2741#define PCLK1 2842#define PCLK2 2943#define HCLK3 3044#define PCLK3 3145#define PCLK4 3246/* AXI and AHB peripheral clocks */47#define USBPHY0 3348#define USBPHY1 3449#define DDR0_GATE 3550#define DDR6_GATE 3651#define CAN0_MUX 3752#define CAN0_DIV 3853#define CAN0_GATE 3954#define CAN1_MUX 4055#define CAN1_DIV 4156#define CAN1_GATE 4257#define CAN2_MUX 4358#define CAN2_DIV 4459#define CAN2_GATE 4560#define CAN3_MUX 4661#define CAN3_DIV 4762#define CAN3_GATE 4863#define SDH0_MUX 4964#define SDH0_GATE 5065#define SDH1_MUX 5166#define SDH1_GATE 5267#define NAND_GATE 5368#define USBD_GATE 5469#define USBH_GATE 5570#define HUSBH0_GATE 5671#define HUSBH1_GATE 5772#define GFX_MUX 5873#define GFX_GATE 5974#define VC8K_GATE 6075#define DCU_MUX 6176#define DCU_GATE 6277#define DCUP_DIV 6378#define EMAC0_GATE 6479#define EMAC1_GATE 6580#define CCAP0_MUX 6681#define CCAP0_DIV 6782#define CCAP0_GATE 6883#define CCAP1_MUX 6984#define CCAP1_DIV 7085#define CCAP1_GATE 7186#define PDMA0_GATE 7287#define PDMA1_GATE 7388#define PDMA2_GATE 7489#define PDMA3_GATE 7590#define WH0_GATE 7691#define WH1_GATE 7792#define HWS_GATE 7893#define EBI_GATE 7994#define SRAM0_GATE 8095#define SRAM1_GATE 8196#define ROM_GATE 8297#define TRA_GATE 8398#define DBG_MUX 8499#define DBG_GATE 85100#define CKO_MUX 86101#define CKO_DIV 87102#define CKO_GATE 88103#define GTMR_GATE 89104#define GPA_GATE 90105#define GPB_GATE 91106#define GPC_GATE 92107#define GPD_GATE 93108#define GPE_GATE 94109#define GPF_GATE 95110#define GPG_GATE 96111#define GPH_GATE 97112#define GPI_GATE 98113#define GPJ_GATE 99114#define GPK_GATE 100115#define GPL_GATE 101116#define GPM_GATE 102117#define GPN_GATE 103118/* APB peripheral clocks */119#define TMR0_MUX 104120#define TMR0_GATE 105121#define TMR1_MUX 106122#define TMR1_GATE 107123#define TMR2_MUX 108124#define TMR2_GATE 109125#define TMR3_MUX 110126#define TMR3_GATE 111127#define TMR4_MUX 112128#define TMR4_GATE 113129#define TMR5_MUX 114130#define TMR5_GATE 115131#define TMR6_MUX 116132#define TMR6_GATE 117133#define TMR7_MUX 118134#define TMR7_GATE 119135#define TMR8_MUX 120136#define TMR8_GATE 121137#define TMR9_MUX 122138#define TMR9_GATE 123139#define TMR10_MUX 124140#define TMR10_GATE 125141#define TMR11_MUX 126142#define TMR11_GATE 127143#define UART0_MUX 128144#define UART0_DIV 129145#define UART0_GATE 130146#define UART1_MUX 131147#define UART1_DIV 132148#define UART1_GATE 133149#define UART2_MUX 134150#define UART2_DIV 135151#define UART2_GATE 136152#define UART3_MUX 137153#define UART3_DIV 138154#define UART3_GATE 139155#define UART4_MUX 140156#define UART4_DIV 141157#define UART4_GATE 142158#define UART5_MUX 143159#define UART5_DIV 144160#define UART5_GATE 145161#define UART6_MUX 146162#define UART6_DIV 147163#define UART6_GATE 148164#define UART7_MUX 149165#define UART7_DIV 150166#define UART7_GATE 151167#define UART8_MUX 152168#define UART8_DIV 153169#define UART8_GATE 154170#define UART9_MUX 155171#define UART9_DIV 156172#define UART9_GATE 157173#define UART10_MUX 158174#define UART10_DIV 159175#define UART10_GATE 160176#define UART11_MUX 161177#define UART11_DIV 162178#define UART11_GATE 163179#define UART12_MUX 164180#define UART12_DIV 165181#define UART12_GATE 166182#define UART13_MUX 167183#define UART13_DIV 168184#define UART13_GATE 169185#define UART14_MUX 170186#define UART14_DIV 171187#define UART14_GATE 172188#define UART15_MUX 173189#define UART15_DIV 174190#define UART15_GATE 175191#define UART16_MUX 176192#define UART16_DIV 177193#define UART16_GATE 178194#define RTC_GATE 179195#define DDR_GATE 180196#define KPI_MUX 181197#define KPI_DIV 182198#define KPI_GATE 183199#define I2C0_GATE 184200#define I2C1_GATE 185201#define I2C2_GATE 186202#define I2C3_GATE 187203#define I2C4_GATE 188204#define I2C5_GATE 189205#define QSPI0_MUX 190206#define QSPI0_GATE 191207#define QSPI1_MUX 192208#define QSPI1_GATE 193209#define SMC0_MUX 194210#define SMC0_DIV 195211#define SMC0_GATE 196212#define SMC1_MUX 197213#define SMC1_DIV 198214#define SMC1_GATE 199215#define WDT0_MUX 200216#define WDT0_GATE 201217#define WDT1_MUX 202218#define WDT1_GATE 203219#define WDT2_MUX 204220#define WDT2_GATE 205221#define WWDT0_MUX 206222#define WWDT1_MUX 207223#define WWDT2_MUX 208224#define EPWM0_GATE 209225#define EPWM1_GATE 210226#define EPWM2_GATE 211227#define I2S0_MUX 212228#define I2S0_GATE 213229#define I2S1_MUX 214230#define I2S1_GATE 215231#define SSMCC_GATE 216232#define SSPCC_GATE 217233#define SPI0_MUX 218234#define SPI0_GATE 219235#define SPI1_MUX 220236#define SPI1_GATE 221237#define SPI2_MUX 222238#define SPI2_GATE 223239#define SPI3_MUX 224240#define SPI3_GATE 225241#define ECAP0_GATE 226242#define ECAP1_GATE 227243#define ECAP2_GATE 228244#define QEI0_GATE 229245#define QEI1_GATE 230246#define QEI2_GATE 231247#define ADC_DIV 232248#define ADC_GATE 233249#define EADC_DIV 234250#define EADC_GATE 235251#define CLK_MAX_IDX 236252 253#endif /* __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H */254