181 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) 2014 Google, Inc.4 */5 6#ifndef _DT_BINDINGS_CLOCK_PISTACHIO_H7#define _DT_BINDINGS_CLOCK_PISTACHIO_H8 9/* PLLs */10#define CLK_MIPS_PLL 011#define CLK_AUDIO_PLL 112#define CLK_RPU_V_PLL 213#define CLK_RPU_L_PLL 314#define CLK_SYS_PLL 415#define CLK_WIFI_PLL 516#define CLK_BT_PLL 617 18/* Fixed-factor clocks */19#define CLK_WIFI_DIV4 1620#define CLK_WIFI_DIV8 1721 22/* Gate clocks */23#define CLK_MIPS 3224#define CLK_AUDIO_IN 3325#define CLK_AUDIO 3426#define CLK_I2S 3527#define CLK_SPDIF 3628#define CLK_AUDIO_DAC 3729#define CLK_RPU_V 3830#define CLK_RPU_L 3931#define CLK_RPU_SLEEP 4032#define CLK_WIFI_PLL_GATE 4133#define CLK_RPU_CORE 4234#define CLK_WIFI_ADC 4335#define CLK_WIFI_DAC 4436#define CLK_USB_PHY 4537#define CLK_ENET_IN 4638#define CLK_ENET 4739#define CLK_UART0 4840#define CLK_UART1 4941#define CLK_PERIPH_SYS 5042#define CLK_SPI0 5143#define CLK_SPI1 5244#define CLK_EVENT_TIMER 5345#define CLK_AUX_ADC_INTERNAL 5446#define CLK_AUX_ADC 5547#define CLK_SD_HOST 5648#define CLK_BT 5749#define CLK_BT_DIV4 5850#define CLK_BT_DIV8 5951#define CLK_BT_1MHZ 6052 53/* Divider clocks */54#define CLK_MIPS_INTERNAL_DIV 6455#define CLK_MIPS_DIV 6556#define CLK_AUDIO_DIV 6657#define CLK_I2S_DIV 6758#define CLK_SPDIF_DIV 6859#define CLK_AUDIO_DAC_DIV 6960#define CLK_RPU_V_DIV 7061#define CLK_RPU_L_DIV 7162#define CLK_RPU_SLEEP_DIV 7263#define CLK_RPU_CORE_DIV 7364#define CLK_USB_PHY_DIV 7465#define CLK_ENET_DIV 7566#define CLK_UART0_INTERNAL_DIV 7667#define CLK_UART0_DIV 7768#define CLK_UART1_INTERNAL_DIV 7869#define CLK_UART1_DIV 7970#define CLK_SYS_INTERNAL_DIV 8071#define CLK_SPI0_INTERNAL_DIV 8172#define CLK_SPI0_DIV 8273#define CLK_SPI1_INTERNAL_DIV 8374#define CLK_SPI1_DIV 8475#define CLK_EVENT_TIMER_INTERNAL_DIV 8576#define CLK_EVENT_TIMER_DIV 8677#define CLK_AUX_ADC_INTERNAL_DIV 8778#define CLK_AUX_ADC_DIV 8879#define CLK_SD_HOST_DIV 8980#define CLK_BT_DIV 9081#define CLK_BT_DIV4_DIV 9182#define CLK_BT_DIV8_DIV 9283#define CLK_BT_1MHZ_INTERNAL_DIV 9384#define CLK_BT_1MHZ_DIV 9485 86/* Mux clocks */87#define CLK_AUDIO_REF_MUX 9688#define CLK_MIPS_PLL_MUX 9789#define CLK_AUDIO_PLL_MUX 9890#define CLK_AUDIO_MUX 9991#define CLK_RPU_V_PLL_MUX 10092#define CLK_RPU_L_PLL_MUX 10193#define CLK_RPU_L_MUX 10294#define CLK_WIFI_PLL_MUX 10395#define CLK_WIFI_DIV4_MUX 10496#define CLK_WIFI_DIV8_MUX 10597#define CLK_RPU_CORE_MUX 10698#define CLK_SYS_PLL_MUX 10799#define CLK_ENET_MUX 108100#define CLK_EVENT_TIMER_MUX 109101#define CLK_SD_HOST_MUX 110102#define CLK_BT_PLL_MUX 111103#define CLK_DEBUG_MUX 112104 105#define CLK_NR_CLKS 113106 107/* Peripheral gate clocks */108#define PERIPH_CLK_SYS 0109#define PERIPH_CLK_SYS_BUS 1110#define PERIPH_CLK_DDR 2111#define PERIPH_CLK_ROM 3112#define PERIPH_CLK_COUNTER_FAST 4113#define PERIPH_CLK_COUNTER_SLOW 5114#define PERIPH_CLK_IR 6115#define PERIPH_CLK_WD 7116#define PERIPH_CLK_PDM 8117#define PERIPH_CLK_PWM 9118#define PERIPH_CLK_I2C0 10119#define PERIPH_CLK_I2C1 11120#define PERIPH_CLK_I2C2 12121#define PERIPH_CLK_I2C3 13122 123/* Peripheral divider clocks */124#define PERIPH_CLK_ROM_DIV 32125#define PERIPH_CLK_COUNTER_FAST_DIV 33126#define PERIPH_CLK_COUNTER_SLOW_PRE_DIV 34127#define PERIPH_CLK_COUNTER_SLOW_DIV 35128#define PERIPH_CLK_IR_PRE_DIV 36129#define PERIPH_CLK_IR_DIV 37130#define PERIPH_CLK_WD_PRE_DIV 38131#define PERIPH_CLK_WD_DIV 39132#define PERIPH_CLK_PDM_PRE_DIV 40133#define PERIPH_CLK_PDM_DIV 41134#define PERIPH_CLK_PWM_PRE_DIV 42135#define PERIPH_CLK_PWM_DIV 43136#define PERIPH_CLK_I2C0_PRE_DIV 44137#define PERIPH_CLK_I2C0_DIV 45138#define PERIPH_CLK_I2C1_PRE_DIV 46139#define PERIPH_CLK_I2C1_DIV 47140#define PERIPH_CLK_I2C2_PRE_DIV 48141#define PERIPH_CLK_I2C2_DIV 49142#define PERIPH_CLK_I2C3_PRE_DIV 50143#define PERIPH_CLK_I2C3_DIV 51144 145#define PERIPH_CLK_NR_CLKS 52146 147/* System gate clocks */148#define SYS_CLK_I2C0 0149#define SYS_CLK_I2C1 1150#define SYS_CLK_I2C2 2151#define SYS_CLK_I2C3 3152#define SYS_CLK_I2S_IN 4153#define SYS_CLK_PAUD_OUT 5154#define SYS_CLK_SPDIF_OUT 6155#define SYS_CLK_SPI0_MASTER 7156#define SYS_CLK_SPI0_SLAVE 8157#define SYS_CLK_PWM 9158#define SYS_CLK_UART0 10159#define SYS_CLK_UART1 11160#define SYS_CLK_SPI1 12161#define SYS_CLK_MDC 13162#define SYS_CLK_SD_HOST 14163#define SYS_CLK_ENET 15164#define SYS_CLK_IR 16165#define SYS_CLK_WD 17166#define SYS_CLK_TIMER 18167#define SYS_CLK_I2S_OUT 24168#define SYS_CLK_SPDIF_IN 25169#define SYS_CLK_EVENT_TIMER 26170#define SYS_CLK_HASH 27171 172#define SYS_CLK_NR_CLKS 28173 174/* Gates for external input clocks */175#define EXT_CLK_AUDIO_IN 0176#define EXT_CLK_ENET_IN 1177 178#define EXT_CLK_NR_CLKS 2179 180#endif /* _DT_BINDINGS_CLOCK_PISTACHIO_H */181