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1/* SPDX-License-Identifier: GPL-2.0 */2 3#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H4#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H5 6/* core clocks */7#define PLL_APLL 18#define PLL_DPLL 29#define PLL_CPLL 310#define PLL_NPLL 411#define APLL_BOOST_H 512#define APLL_BOOST_L 613#define ARMCLK 714 15/* sclk gates (special clocks) */16#define USB480M 1417#define SCLK_PDM 1518#define SCLK_I2S0_TX 1619#define SCLK_I2S0_TX_OUT 1720#define SCLK_I2S0_RX 1821#define SCLK_I2S0_RX_OUT 1922#define SCLK_I2S1 2023#define SCLK_I2S1_OUT 2124#define SCLK_I2S2 2225#define SCLK_I2S2_OUT 2326#define SCLK_UART1 2427#define SCLK_UART2 2528#define SCLK_UART3 2629#define SCLK_UART4 2730#define SCLK_UART5 2831#define SCLK_I2C0 2932#define SCLK_I2C1 3033#define SCLK_I2C2 3134#define SCLK_I2C3 3235#define SCLK_I2C4 3336#define SCLK_PWM0 3437#define SCLK_PWM1 3538#define SCLK_SPI0 3639#define SCLK_SPI1 3740#define SCLK_TIMER0 3841#define SCLK_TIMER1 3942#define SCLK_TIMER2 4043#define SCLK_TIMER3 4144#define SCLK_TIMER4 4245#define SCLK_TIMER5 4346#define SCLK_TSADC 4447#define SCLK_SARADC 4548#define SCLK_OTP 4649#define SCLK_OTP_USR 4750#define SCLK_CRYPTO 4851#define SCLK_CRYPTO_APK 4952#define SCLK_DDRC 5053#define SCLK_ISP 5154#define SCLK_CIF_OUT 5255#define SCLK_RGA_CORE 5356#define SCLK_VOPB_PWM 5457#define SCLK_NANDC 5558#define SCLK_SDIO 5659#define SCLK_EMMC 5760#define SCLK_SFC 5861#define SCLK_SDMMC 5962#define SCLK_OTG_ADP 6063#define SCLK_GMAC_SRC 6164#define SCLK_GMAC 6265#define SCLK_GMAC_RX_TX 6366#define SCLK_MAC_REF 6467#define SCLK_MAC_REFOUT 6568#define SCLK_MAC_OUT 6669#define SCLK_SDMMC_DRV 6770#define SCLK_SDMMC_SAMPLE 6871#define SCLK_SDIO_DRV 6972#define SCLK_SDIO_SAMPLE 7073#define SCLK_EMMC_DRV 7174#define SCLK_EMMC_SAMPLE 7275#define SCLK_GPU 7376#define SCLK_PVTM 7477#define SCLK_CORE_VPU 7578#define SCLK_GMAC_RMII 7679#define SCLK_UART2_SRC 7780#define SCLK_NANDC_DIV 7881#define SCLK_NANDC_DIV50 7982#define SCLK_SDIO_DIV 8083#define SCLK_SDIO_DIV50 8184#define SCLK_EMMC_DIV 8285#define SCLK_EMMC_DIV50 8386#define SCLK_DDRCLK 8487#define SCLK_UART1_SRC 8588#define SCLK_SDMMC_DIV 8689#define SCLK_SDMMC_DIV50 8790 91/* dclk gates */92#define DCLK_VOPB 15093#define DCLK_VOPL 15194 95/* aclk gates */96#define ACLK_GPU 17097#define ACLK_BUS_PRE 17198#define ACLK_CRYPTO 17299#define ACLK_VI_PRE 173100#define ACLK_VO_PRE 174101#define ACLK_VPU 175102#define ACLK_PERI_PRE 176103#define ACLK_GMAC 178104#define ACLK_CIF 179105#define ACLK_ISP 180106#define ACLK_VOPB 181107#define ACLK_VOPL 182108#define ACLK_RGA 183109#define ACLK_GIC 184110#define ACLK_DCF 186111#define ACLK_DMAC 187112#define ACLK_BUS_SRC 188113#define ACLK_PERI_SRC 189114 115/* hclk gates */116#define HCLK_BUS_PRE 240117#define HCLK_CRYPTO 241118#define HCLK_VI_PRE 242119#define HCLK_VO_PRE 243120#define HCLK_VPU 244121#define HCLK_PERI_PRE 245122#define HCLK_MMC_NAND 246123#define HCLK_SDMMC 247124#define HCLK_USB 248125#define HCLK_CIF 249126#define HCLK_ISP 250127#define HCLK_VOPB 251128#define HCLK_VOPL 252129#define HCLK_RGA 253130#define HCLK_NANDC 254131#define HCLK_SDIO 255132#define HCLK_EMMC 256133#define HCLK_SFC 257134#define HCLK_OTG 258135#define HCLK_HOST 259136#define HCLK_HOST_ARB 260137#define HCLK_PDM 261138#define HCLK_I2S0 262139#define HCLK_I2S1 263140#define HCLK_I2S2 264141 142/* pclk gates */143#define PCLK_BUS_PRE 320144#define PCLK_DDR 321145#define PCLK_VO_PRE 322146#define PCLK_GMAC 323147#define PCLK_MIPI_DSI 324148#define PCLK_MIPIDSIPHY 325149#define PCLK_MIPICSIPHY 326150#define PCLK_USB_GRF 327151#define PCLK_DCF 328152#define PCLK_UART1 329153#define PCLK_UART2 330154#define PCLK_UART3 331155#define PCLK_UART4 332156#define PCLK_UART5 333157#define PCLK_I2C0 334158#define PCLK_I2C1 335159#define PCLK_I2C2 336160#define PCLK_I2C3 337161#define PCLK_I2C4 338162#define PCLK_PWM0 339163#define PCLK_PWM1 340164#define PCLK_SPI0 341165#define PCLK_SPI1 342166#define PCLK_SARADC 343167#define PCLK_TSADC 344168#define PCLK_TIMER 345169#define PCLK_OTP_NS 346170#define PCLK_WDT_NS 347171#define PCLK_GPIO1 348172#define PCLK_GPIO2 349173#define PCLK_GPIO3 350174#define PCLK_ISP 351175#define PCLK_CIF 352176#define PCLK_OTP_PHY 353177 178/* pmu-clocks indices */179 180#define PLL_GPLL 1181 182#define SCLK_RTC32K_PMU 4183#define SCLK_WIFI_PMU 5184#define SCLK_UART0_PMU 6185#define SCLK_PVTM_PMU 7186#define PCLK_PMU_PRE 8187#define SCLK_REF24M_PMU 9188#define SCLK_USBPHY_REF 10189#define SCLK_MIPIDSIPHY_REF 11190 191#define XIN24M_DIV 12192 193#define PCLK_GPIO0_PMU 20194#define PCLK_UART0_PMU 21195 196/* soft-reset indices */197#define SRST_CORE0_PO 0198#define SRST_CORE1_PO 1199#define SRST_CORE2_PO 2200#define SRST_CORE3_PO 3201#define SRST_CORE0 4202#define SRST_CORE1 5203#define SRST_CORE2 6204#define SRST_CORE3 7205#define SRST_CORE0_DBG 8206#define SRST_CORE1_DBG 9207#define SRST_CORE2_DBG 10208#define SRST_CORE3_DBG 11209#define SRST_TOPDBG 12210#define SRST_CORE_NOC 13211#define SRST_STRC_A 14212#define SRST_L2C 15213 214#define SRST_DAP 16215#define SRST_CORE_PVTM 17216#define SRST_GPU 18217#define SRST_GPU_NIU 19218#define SRST_UPCTL2 20219#define SRST_UPCTL2_A 21220#define SRST_UPCTL2_P 22221#define SRST_MSCH 23222#define SRST_MSCH_P 24223#define SRST_DDRMON_P 25224#define SRST_DDRSTDBY_P 26225#define SRST_DDRSTDBY 27226#define SRST_DDRGRF_p 28227#define SRST_AXI_SPLIT_A 29228#define SRST_AXI_CMD_A 30229#define SRST_AXI_CMD_P 31230 231#define SRST_DDRPHY 32232#define SRST_DDRPHYDIV 33233#define SRST_DDRPHY_P 34234#define SRST_VPU_A 36235#define SRST_VPU_NIU_A 37236#define SRST_VPU_H 38237#define SRST_VPU_NIU_H 39238#define SRST_VI_NIU_A 40239#define SRST_VI_NIU_H 41240#define SRST_ISP_H 42241#define SRST_ISP 43242#define SRST_CIF_A 44243#define SRST_CIF_H 45244#define SRST_CIF_PCLKIN 46245#define SRST_MIPICSIPHY_P 47246 247#define SRST_VO_NIU_A 48248#define SRST_VO_NIU_H 49249#define SRST_VO_NIU_P 50250#define SRST_VOPB_A 51251#define SRST_VOPB_H 52252#define SRST_VOPB 53253#define SRST_PWM_VOPB 54254#define SRST_VOPL_A 55255#define SRST_VOPL_H 56256#define SRST_VOPL 57257#define SRST_RGA_A 58258#define SRST_RGA_H 59259#define SRST_RGA 60260#define SRST_MIPIDSI_HOST_P 61261#define SRST_MIPIDSIPHY_P 62262#define SRST_VPU_CORE 63263 264#define SRST_PERI_NIU_A 64265#define SRST_USB_NIU_H 65266#define SRST_USB2OTG_H 66267#define SRST_USB2OTG 67268#define SRST_USB2OTG_ADP 68269#define SRST_USB2HOST_H 69270#define SRST_USB2HOST_ARB_H 70271#define SRST_USB2HOST_AUX_H 71272#define SRST_USB2HOST_EHCI 72273#define SRST_USB2HOST 73274#define SRST_USBPHYPOR 74275#define SRST_USBPHY_OTG_PORT 75276#define SRST_USBPHY_HOST_PORT 76277#define SRST_USBPHY_GRF 77278#define SRST_CPU_BOOST_P 78279#define SRST_CPU_BOOST 79280 281#define SRST_MMC_NAND_NIU_H 80282#define SRST_SDIO_H 81283#define SRST_EMMC_H 82284#define SRST_SFC_H 83285#define SRST_SFC 84286#define SRST_SDCARD_NIU_H 85287#define SRST_SDMMC_H 86288#define SRST_NANDC_H 89289#define SRST_NANDC 90290#define SRST_GMAC_NIU_A 92291#define SRST_GMAC_NIU_P 93292#define SRST_GMAC_A 94293 294#define SRST_PMU_NIU_P 96295#define SRST_PMU_SGRF_P 97296#define SRST_PMU_GRF_P 98297#define SRST_PMU 99298#define SRST_PMU_MEM_P 100299#define SRST_PMU_GPIO0_P 101300#define SRST_PMU_UART0_P 102301#define SRST_PMU_CRU_P 103302#define SRST_PMU_PVTM 104303#define SRST_PMU_UART 105304#define SRST_PMU_NIU_H 106305#define SRST_PMU_DDR_FAIL_SAVE 107306#define SRST_PMU_CORE_PERF_A 108307#define SRST_PMU_CORE_GRF_P 109308#define SRST_PMU_GPU_PERF_A 110309#define SRST_PMU_GPU_GRF_P 111310 311#define SRST_CRYPTO_NIU_A 112312#define SRST_CRYPTO_NIU_H 113313#define SRST_CRYPTO_A 114314#define SRST_CRYPTO_H 115315#define SRST_CRYPTO 116316#define SRST_CRYPTO_APK 117317#define SRST_BUS_NIU_H 120318#define SRST_USB_NIU_P 121319#define SRST_BUS_TOP_NIU_P 122320#define SRST_INTMEM_A 123321#define SRST_GIC_A 124322#define SRST_ROM_H 126323#define SRST_DCF_A 127324 325#define SRST_DCF_P 128326#define SRST_PDM_H 129327#define SRST_PDM 130328#define SRST_I2S0_H 131329#define SRST_I2S0_TX 132330#define SRST_I2S1_H 133331#define SRST_I2S1 134332#define SRST_I2S2_H 135333#define SRST_I2S2 136334#define SRST_UART1_P 137335#define SRST_UART1 138336#define SRST_UART2_P 139337#define SRST_UART2 140338#define SRST_UART3_P 141339#define SRST_UART3 142340#define SRST_UART4_P 143341 342#define SRST_UART4 144343#define SRST_UART5_P 145344#define SRST_UART5 146345#define SRST_I2C0_P 147346#define SRST_I2C0 148347#define SRST_I2C1_P 149348#define SRST_I2C1 150349#define SRST_I2C2_P 151350#define SRST_I2C2 152351#define SRST_I2C3_P 153352#define SRST_I2C3 154353#define SRST_PWM0_P 157354#define SRST_PWM0 158355#define SRST_PWM1_P 159356 357#define SRST_PWM1 160358#define SRST_SPI0_P 161359#define SRST_SPI0 162360#define SRST_SPI1_P 163361#define SRST_SPI1 164362#define SRST_SARADC_P 165363#define SRST_SARADC 166364#define SRST_TSADC_P 167365#define SRST_TSADC 168366#define SRST_TIMER_P 169367#define SRST_TIMER0 170368#define SRST_TIMER1 171369#define SRST_TIMER2 172370#define SRST_TIMER3 173371#define SRST_TIMER4 174372#define SRST_TIMER5 175373 374#define SRST_OTP_NS_P 176375#define SRST_OTP_NS_SBPI 177376#define SRST_OTP_NS_USR 178377#define SRST_OTP_PHY_P 179378#define SRST_OTP_PHY 180379#define SRST_WDT_NS_P 181380#define SRST_GPIO1_P 182381#define SRST_GPIO2_P 183382#define SRST_GPIO3_P 184383#define SRST_SGRF_P 185384#define SRST_GRF_P 186385#define SRST_I2S0_RX 191386 387#endif388