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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.4 */5 6#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H7#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H8 9/* DISP_CC clock registers */10#define DISP_CC_MDSS_AHB_CLK 011#define DISP_CC_MDSS_AHB_CLK_SRC 112#define DISP_CC_MDSS_BYTE0_CLK 213#define DISP_CC_MDSS_BYTE0_CLK_SRC 314#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 415#define DISP_CC_MDSS_BYTE0_INTF_CLK 516#define DISP_CC_MDSS_BYTE1_CLK 617#define DISP_CC_MDSS_BYTE1_CLK_SRC 718#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 819#define DISP_CC_MDSS_BYTE1_INTF_CLK 920#define DISP_CC_MDSS_DP_AUX1_CLK 1021#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 1122#define DISP_CC_MDSS_DP_AUX_CLK 1223#define DISP_CC_MDSS_DP_AUX_CLK_SRC 1324#define DISP_CC_MDSS_DP_LINK1_CLK 1425#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 1526#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 1627#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 1728#define DISP_CC_MDSS_DP_LINK_CLK 1829#define DISP_CC_MDSS_DP_LINK_CLK_SRC 1930#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 2031#define DISP_CC_MDSS_DP_LINK_INTF_CLK 2132#define DISP_CC_MDSS_DP_PIXEL1_CLK 2233#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 2334#define DISP_CC_MDSS_DP_PIXEL2_CLK 2435#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 2536#define DISP_CC_MDSS_DP_PIXEL_CLK 2637#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 2738#define DISP_CC_MDSS_ESC0_CLK 2839#define DISP_CC_MDSS_ESC0_CLK_SRC 2940#define DISP_CC_MDSS_ESC1_CLK 3041#define DISP_CC_MDSS_ESC1_CLK_SRC 3142#define DISP_CC_MDSS_MDP_CLK 3243#define DISP_CC_MDSS_MDP_CLK_SRC 3344#define DISP_CC_MDSS_MDP_LUT_CLK 3445#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 3546#define DISP_CC_MDSS_PCLK0_CLK 3647#define DISP_CC_MDSS_PCLK0_CLK_SRC 3748#define DISP_CC_MDSS_PCLK1_CLK 3849#define DISP_CC_MDSS_PCLK1_CLK_SRC 3950#define DISP_CC_MDSS_ROT_CLK 4051#define DISP_CC_MDSS_ROT_CLK_SRC 4152#define DISP_CC_MDSS_RSCC_AHB_CLK 4253#define DISP_CC_MDSS_RSCC_VSYNC_CLK 4354#define DISP_CC_MDSS_VSYNC_CLK 4455#define DISP_CC_MDSS_VSYNC_CLK_SRC 4556#define DISP_CC_PLL0 4657#define DISP_CC_PLL1 4758#define DISP_CC_MDSS_EDP_AUX_CLK 4859#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 4960#define DISP_CC_MDSS_EDP_GTC_CLK 5061#define DISP_CC_MDSS_EDP_GTC_CLK_SRC 5162#define DISP_CC_MDSS_EDP_LINK_CLK 5263#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 5364#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 5465#define DISP_CC_MDSS_EDP_PIXEL_CLK 5566#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 5667#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 5768 69/* DISP_CC Reset */70#define DISP_CC_MDSS_CORE_BCR 071#define DISP_CC_MDSS_RSCC_BCR 172 73/* DISP_CC GDSCR */74#define MDSS_GDSC 075 76#endif77