176 lines · c
1/* Copyright (c) 2015 The Linux Foundation. All rights reserved.2 *3 * Permission to use, copy, modify, and/or distribute this software for any4 * purpose with or without fee is hereby granted, provided that the above5 * copyright notice and this permission notice appear in all copies.6 *7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR10 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN12 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF13 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.14 *15 */16#ifndef __QCOM_CLK_IPQ4019_H__17#define __QCOM_CLK_IPQ4019_H__18 19#define GCC_DUMMY_CLK 020#define AUDIO_CLK_SRC 121#define BLSP1_QUP1_I2C_APPS_CLK_SRC 222#define BLSP1_QUP1_SPI_APPS_CLK_SRC 323#define BLSP1_QUP2_I2C_APPS_CLK_SRC 424#define BLSP1_QUP2_SPI_APPS_CLK_SRC 525#define BLSP1_UART1_APPS_CLK_SRC 626#define BLSP1_UART2_APPS_CLK_SRC 727#define GCC_USB3_MOCK_UTMI_CLK_SRC 828#define GCC_APPS_CLK_SRC 929#define GCC_APPS_AHB_CLK_SRC 1030#define GP1_CLK_SRC 1131#define GP2_CLK_SRC 1232#define GP3_CLK_SRC 1333#define SDCC1_APPS_CLK_SRC 1434#define FEPHY_125M_DLY_CLK_SRC 1535#define WCSS2G_CLK_SRC 1636#define WCSS5G_CLK_SRC 1737#define GCC_APSS_AHB_CLK 1838#define GCC_AUDIO_AHB_CLK 1939#define GCC_AUDIO_PWM_CLK 2040#define GCC_BLSP1_AHB_CLK 2141#define GCC_BLSP1_QUP1_I2C_APPS_CLK 2242#define GCC_BLSP1_QUP1_SPI_APPS_CLK 2343#define GCC_BLSP1_QUP2_I2C_APPS_CLK 2444#define GCC_BLSP1_QUP2_SPI_APPS_CLK 2545#define GCC_BLSP1_UART1_APPS_CLK 2646#define GCC_BLSP1_UART2_APPS_CLK 2747#define GCC_DCD_XO_CLK 2848#define GCC_GP1_CLK 2949#define GCC_GP2_CLK 3050#define GCC_GP3_CLK 3151#define GCC_BOOT_ROM_AHB_CLK 3252#define GCC_CRYPTO_AHB_CLK 3353#define GCC_CRYPTO_AXI_CLK 3454#define GCC_CRYPTO_CLK 3555#define GCC_ESS_CLK 3656#define GCC_IMEM_AXI_CLK 3757#define GCC_IMEM_CFG_AHB_CLK 3858#define GCC_PCIE_AHB_CLK 3959#define GCC_PCIE_AXI_M_CLK 4060#define GCC_PCIE_AXI_S_CLK 4161#define GCC_PCNOC_AHB_CLK 4262#define GCC_PRNG_AHB_CLK 4363#define GCC_QPIC_AHB_CLK 4464#define GCC_QPIC_CLK 4565#define GCC_SDCC1_AHB_CLK 4666#define GCC_SDCC1_APPS_CLK 4767#define GCC_SNOC_PCNOC_AHB_CLK 4868#define GCC_SYS_NOC_125M_CLK 4969#define GCC_SYS_NOC_AXI_CLK 5070#define GCC_TCSR_AHB_CLK 5171#define GCC_TLMM_AHB_CLK 5272#define GCC_USB2_MASTER_CLK 5373#define GCC_USB2_SLEEP_CLK 5474#define GCC_USB2_MOCK_UTMI_CLK 5575#define GCC_USB3_MASTER_CLK 5676#define GCC_USB3_SLEEP_CLK 5777#define GCC_USB3_MOCK_UTMI_CLK 5878#define GCC_WCSS2G_CLK 5979#define GCC_WCSS2G_REF_CLK 6080#define GCC_WCSS2G_RTC_CLK 6181#define GCC_WCSS5G_CLK 6282#define GCC_WCSS5G_REF_CLK 6383#define GCC_WCSS5G_RTC_CLK 6484#define GCC_APSS_DDRPLL_VCO 6585#define GCC_SDCC_PLLDIV_CLK 6686#define GCC_FEPLL_VCO 6787#define GCC_FEPLL125_CLK 6888#define GCC_FEPLL125DLY_CLK 6989#define GCC_FEPLL200_CLK 7090#define GCC_FEPLL500_CLK 7191#define GCC_FEPLL_WCSS2G_CLK 7292#define GCC_FEPLL_WCSS5G_CLK 7393#define GCC_APSS_CPU_PLLDIV_CLK 7494#define GCC_PCNOC_AHB_CLK_SRC 7595 96#define WIFI0_CPU_INIT_RESET 097#define WIFI0_RADIO_SRIF_RESET 198#define WIFI0_RADIO_WARM_RESET 299#define WIFI0_RADIO_COLD_RESET 3100#define WIFI0_CORE_WARM_RESET 4101#define WIFI0_CORE_COLD_RESET 5102#define WIFI1_CPU_INIT_RESET 6103#define WIFI1_RADIO_SRIF_RESET 7104#define WIFI1_RADIO_WARM_RESET 8105#define WIFI1_RADIO_COLD_RESET 9106#define WIFI1_CORE_WARM_RESET 10107#define WIFI1_CORE_COLD_RESET 11108#define USB3_UNIPHY_PHY_ARES 12109#define USB3_HSPHY_POR_ARES 13110#define USB3_HSPHY_S_ARES 14111#define USB2_HSPHY_POR_ARES 15112#define USB2_HSPHY_S_ARES 16113#define PCIE_PHY_AHB_ARES 17114#define PCIE_AHB_ARES 18115#define PCIE_PWR_ARES 19116#define PCIE_PIPE_STICKY_ARES 20117#define PCIE_AXI_M_STICKY_ARES 21118#define PCIE_PHY_ARES 22119#define PCIE_PARF_XPU_ARES 23120#define PCIE_AXI_S_XPU_ARES 24121#define PCIE_AXI_M_VMIDMT_ARES 25122#define PCIE_PIPE_ARES 26123#define PCIE_AXI_S_ARES 27124#define PCIE_AXI_M_ARES 28125#define ESS_RESET 29126#define GCC_BLSP1_BCR 30127#define GCC_BLSP1_QUP1_BCR 31128#define GCC_BLSP1_UART1_BCR 32129#define GCC_BLSP1_QUP2_BCR 33130#define GCC_BLSP1_UART2_BCR 34131#define GCC_BIMC_BCR 35132#define GCC_TLMM_BCR 36133#define GCC_IMEM_BCR 37134#define GCC_ESS_BCR 38135#define GCC_PRNG_BCR 39136#define GCC_BOOT_ROM_BCR 40137#define GCC_CRYPTO_BCR 41138#define GCC_SDCC1_BCR 42139#define GCC_SEC_CTRL_BCR 43140#define GCC_AUDIO_BCR 44141#define GCC_QPIC_BCR 45142#define GCC_PCIE_BCR 46143#define GCC_USB2_BCR 47144#define GCC_USB2_PHY_BCR 48145#define GCC_USB3_BCR 49146#define GCC_USB3_PHY_BCR 50147#define GCC_SYSTEM_NOC_BCR 51148#define GCC_PCNOC_BCR 52149#define GCC_DCD_BCR 53150#define GCC_SNOC_BUS_TIMEOUT0_BCR 54151#define GCC_SNOC_BUS_TIMEOUT1_BCR 55152#define GCC_SNOC_BUS_TIMEOUT2_BCR 56153#define GCC_SNOC_BUS_TIMEOUT3_BCR 57154#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58155#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59156#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60157#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61158#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62159#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63160#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64161#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65162#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66163#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67164#define GCC_TCSR_BCR 68165#define GCC_QDSS_BCR 69166#define GCC_MPM_BCR 70167#define GCC_SPDM_BCR 71168#define ESS_MAC1_ARES 72169#define ESS_MAC2_ARES 73170#define ESS_MAC3_ARES 74171#define ESS_MAC4_ARES 75172#define ESS_MAC5_ARES 76173#define ESS_PSGMII_ARES 77174 175#endif176