389 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.4 */5 6#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H7#define _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H8 9#define GPLL0 010#define GPLL0_MAIN 111#define GCC_SLEEP_CLK_SRC 212#define BLSP1_QUP1_I2C_APPS_CLK_SRC 313#define BLSP1_QUP1_SPI_APPS_CLK_SRC 414#define BLSP1_QUP2_I2C_APPS_CLK_SRC 515#define BLSP1_QUP2_SPI_APPS_CLK_SRC 616#define BLSP1_QUP3_I2C_APPS_CLK_SRC 717#define BLSP1_QUP3_SPI_APPS_CLK_SRC 818#define BLSP1_QUP4_I2C_APPS_CLK_SRC 919#define BLSP1_QUP4_SPI_APPS_CLK_SRC 1020#define BLSP1_QUP5_I2C_APPS_CLK_SRC 1121#define BLSP1_QUP5_SPI_APPS_CLK_SRC 1222#define BLSP1_QUP6_I2C_APPS_CLK_SRC 1323#define BLSP1_QUP6_SPI_APPS_CLK_SRC 1424#define BLSP1_UART1_APPS_CLK_SRC 1525#define BLSP1_UART2_APPS_CLK_SRC 1626#define BLSP1_UART3_APPS_CLK_SRC 1727#define BLSP1_UART4_APPS_CLK_SRC 1828#define BLSP1_UART5_APPS_CLK_SRC 1929#define BLSP1_UART6_APPS_CLK_SRC 2030#define GCC_BLSP1_AHB_CLK 2131#define GCC_BLSP1_QUP1_I2C_APPS_CLK 2232#define GCC_BLSP1_QUP1_SPI_APPS_CLK 2333#define GCC_BLSP1_QUP2_I2C_APPS_CLK 2434#define GCC_BLSP1_QUP2_SPI_APPS_CLK 2535#define GCC_BLSP1_QUP3_I2C_APPS_CLK 2636#define GCC_BLSP1_QUP3_SPI_APPS_CLK 2737#define GCC_BLSP1_QUP4_I2C_APPS_CLK 2838#define GCC_BLSP1_QUP4_SPI_APPS_CLK 2939#define GCC_BLSP1_QUP5_I2C_APPS_CLK 3040#define GCC_BLSP1_QUP5_SPI_APPS_CLK 3141#define GCC_BLSP1_QUP6_I2C_APPS_CLK 3242#define GCC_BLSP1_QUP6_SPI_APPS_CLK 3343#define GCC_BLSP1_UART1_APPS_CLK 3444#define GCC_BLSP1_UART2_APPS_CLK 3545#define GCC_BLSP1_UART3_APPS_CLK 3646#define GCC_BLSP1_UART4_APPS_CLK 3747#define GCC_BLSP1_UART5_APPS_CLK 3848#define GCC_BLSP1_UART6_APPS_CLK 3949#define GCC_PRNG_AHB_CLK 4050#define GCC_QPIC_AHB_CLK 4151#define GCC_QPIC_CLK 4252#define PCNOC_BFDCD_CLK_SRC 4353#define GPLL2_MAIN 4454#define GPLL2 4555#define GPLL4_MAIN 4656#define GPLL4 4757#define GPLL6_MAIN 4858#define GPLL6 4959#define UBI32_PLL_MAIN 5060#define UBI32_PLL 5161#define NSS_CRYPTO_PLL_MAIN 5262#define NSS_CRYPTO_PLL 5363#define PCIE0_AXI_CLK_SRC 5464#define PCIE0_AUX_CLK_SRC 5565#define PCIE0_PIPE_CLK_SRC 5666#define PCIE1_AXI_CLK_SRC 5767#define PCIE1_AUX_CLK_SRC 5868#define PCIE1_PIPE_CLK_SRC 5969#define SDCC1_APPS_CLK_SRC 6070#define SDCC1_ICE_CORE_CLK_SRC 6171#define SDCC2_APPS_CLK_SRC 6272#define USB0_MASTER_CLK_SRC 6373#define USB0_AUX_CLK_SRC 6474#define USB0_MOCK_UTMI_CLK_SRC 6575#define USB0_PIPE_CLK_SRC 6676#define USB1_MASTER_CLK_SRC 6777#define USB1_AUX_CLK_SRC 6878#define USB1_MOCK_UTMI_CLK_SRC 6979#define USB1_PIPE_CLK_SRC 7080#define GCC_XO_CLK_SRC 7181#define SYSTEM_NOC_BFDCD_CLK_SRC 7282#define NSS_CE_CLK_SRC 7383#define NSS_NOC_BFDCD_CLK_SRC 7484#define NSS_CRYPTO_CLK_SRC 7585#define NSS_UBI0_CLK_SRC 7686#define NSS_UBI0_DIV_CLK_SRC 7787#define NSS_UBI1_CLK_SRC 7888#define NSS_UBI1_DIV_CLK_SRC 7989#define UBI_MPT_CLK_SRC 8090#define NSS_IMEM_CLK_SRC 8191#define NSS_PPE_CLK_SRC 8292#define NSS_PORT1_RX_CLK_SRC 8393#define NSS_PORT1_RX_DIV_CLK_SRC 8494#define NSS_PORT1_TX_CLK_SRC 8595#define NSS_PORT1_TX_DIV_CLK_SRC 8696#define NSS_PORT2_RX_CLK_SRC 8797#define NSS_PORT2_RX_DIV_CLK_SRC 8898#define NSS_PORT2_TX_CLK_SRC 8999#define NSS_PORT2_TX_DIV_CLK_SRC 90100#define NSS_PORT3_RX_CLK_SRC 91101#define NSS_PORT3_RX_DIV_CLK_SRC 92102#define NSS_PORT3_TX_CLK_SRC 93103#define NSS_PORT3_TX_DIV_CLK_SRC 94104#define NSS_PORT4_RX_CLK_SRC 95105#define NSS_PORT4_RX_DIV_CLK_SRC 96106#define NSS_PORT4_TX_CLK_SRC 97107#define NSS_PORT4_TX_DIV_CLK_SRC 98108#define NSS_PORT5_RX_CLK_SRC 99109#define NSS_PORT5_RX_DIV_CLK_SRC 100110#define NSS_PORT5_TX_CLK_SRC 101111#define NSS_PORT5_TX_DIV_CLK_SRC 102112#define NSS_PORT6_RX_CLK_SRC 103113#define NSS_PORT6_RX_DIV_CLK_SRC 104114#define NSS_PORT6_TX_CLK_SRC 105115#define NSS_PORT6_TX_DIV_CLK_SRC 106116#define CRYPTO_CLK_SRC 107117#define GP1_CLK_SRC 108118#define GP2_CLK_SRC 109119#define GP3_CLK_SRC 110120#define GCC_PCIE0_AHB_CLK 111121#define GCC_PCIE0_AUX_CLK 112122#define GCC_PCIE0_AXI_M_CLK 113123#define GCC_PCIE0_AXI_S_CLK 114124#define GCC_PCIE0_PIPE_CLK 115125#define GCC_SYS_NOC_PCIE0_AXI_CLK 116126#define GCC_PCIE1_AHB_CLK 117127#define GCC_PCIE1_AUX_CLK 118128#define GCC_PCIE1_AXI_M_CLK 119129#define GCC_PCIE1_AXI_S_CLK 120130#define GCC_PCIE1_PIPE_CLK 121131#define GCC_SYS_NOC_PCIE1_AXI_CLK 122132#define GCC_USB0_AUX_CLK 123133#define GCC_SYS_NOC_USB0_AXI_CLK 124134#define GCC_USB0_MASTER_CLK 125135#define GCC_USB0_MOCK_UTMI_CLK 126136#define GCC_USB0_PHY_CFG_AHB_CLK 127137#define GCC_USB0_PIPE_CLK 128138#define GCC_USB0_SLEEP_CLK 129139#define GCC_USB1_AUX_CLK 130140#define GCC_SYS_NOC_USB1_AXI_CLK 131141#define GCC_USB1_MASTER_CLK 132142#define GCC_USB1_MOCK_UTMI_CLK 133143#define GCC_USB1_PHY_CFG_AHB_CLK 134144#define GCC_USB1_PIPE_CLK 135145#define GCC_USB1_SLEEP_CLK 136146#define GCC_SDCC1_AHB_CLK 137147#define GCC_SDCC1_APPS_CLK 138148#define GCC_SDCC1_ICE_CORE_CLK 139149#define GCC_SDCC2_AHB_CLK 140150#define GCC_SDCC2_APPS_CLK 141151#define GCC_MEM_NOC_NSS_AXI_CLK 142152#define GCC_NSS_CE_APB_CLK 143153#define GCC_NSS_CE_AXI_CLK 144154#define GCC_NSS_CFG_CLK 145155#define GCC_NSS_CRYPTO_CLK 146156#define GCC_NSS_CSR_CLK 147157#define GCC_NSS_EDMA_CFG_CLK 148158#define GCC_NSS_EDMA_CLK 149159#define GCC_NSS_IMEM_CLK 150160#define GCC_NSS_NOC_CLK 151161#define GCC_NSS_PPE_BTQ_CLK 152162#define GCC_NSS_PPE_CFG_CLK 153163#define GCC_NSS_PPE_CLK 154164#define GCC_NSS_PPE_IPE_CLK 155165#define GCC_NSS_PTP_REF_CLK 156166#define GCC_NSSNOC_CE_APB_CLK 157167#define GCC_NSSNOC_CE_AXI_CLK 158168#define GCC_NSSNOC_CRYPTO_CLK 159169#define GCC_NSSNOC_PPE_CFG_CLK 160170#define GCC_NSSNOC_PPE_CLK 161171#define GCC_NSSNOC_QOSGEN_REF_CLK 162172#define GCC_NSSNOC_SNOC_CLK 163173#define GCC_NSSNOC_TIMEOUT_REF_CLK 164174#define GCC_NSSNOC_UBI0_AHB_CLK 165175#define GCC_NSSNOC_UBI1_AHB_CLK 166176#define GCC_UBI0_AHB_CLK 167177#define GCC_UBI0_AXI_CLK 168178#define GCC_UBI0_NC_AXI_CLK 169179#define GCC_UBI0_CORE_CLK 170180#define GCC_UBI0_MPT_CLK 171181#define GCC_UBI1_AHB_CLK 172182#define GCC_UBI1_AXI_CLK 173183#define GCC_UBI1_NC_AXI_CLK 174184#define GCC_UBI1_CORE_CLK 175185#define GCC_UBI1_MPT_CLK 176186#define GCC_CMN_12GPLL_AHB_CLK 177187#define GCC_CMN_12GPLL_SYS_CLK 178188#define GCC_MDIO_AHB_CLK 179189#define GCC_UNIPHY0_AHB_CLK 180190#define GCC_UNIPHY0_SYS_CLK 181191#define GCC_UNIPHY1_AHB_CLK 182192#define GCC_UNIPHY1_SYS_CLK 183193#define GCC_UNIPHY2_AHB_CLK 184194#define GCC_UNIPHY2_SYS_CLK 185195#define GCC_NSS_PORT1_RX_CLK 186196#define GCC_NSS_PORT1_TX_CLK 187197#define GCC_NSS_PORT2_RX_CLK 188198#define GCC_NSS_PORT2_TX_CLK 189199#define GCC_NSS_PORT3_RX_CLK 190200#define GCC_NSS_PORT3_TX_CLK 191201#define GCC_NSS_PORT4_RX_CLK 192202#define GCC_NSS_PORT4_TX_CLK 193203#define GCC_NSS_PORT5_RX_CLK 194204#define GCC_NSS_PORT5_TX_CLK 195205#define GCC_NSS_PORT6_RX_CLK 196206#define GCC_NSS_PORT6_TX_CLK 197207#define GCC_PORT1_MAC_CLK 198208#define GCC_PORT2_MAC_CLK 199209#define GCC_PORT3_MAC_CLK 200210#define GCC_PORT4_MAC_CLK 201211#define GCC_PORT5_MAC_CLK 202212#define GCC_PORT6_MAC_CLK 203213#define GCC_UNIPHY0_PORT1_RX_CLK 204214#define GCC_UNIPHY0_PORT1_TX_CLK 205215#define GCC_UNIPHY0_PORT2_RX_CLK 206216#define GCC_UNIPHY0_PORT2_TX_CLK 207217#define GCC_UNIPHY0_PORT3_RX_CLK 208218#define GCC_UNIPHY0_PORT3_TX_CLK 209219#define GCC_UNIPHY0_PORT4_RX_CLK 210220#define GCC_UNIPHY0_PORT4_TX_CLK 211221#define GCC_UNIPHY0_PORT5_RX_CLK 212222#define GCC_UNIPHY0_PORT5_TX_CLK 213223#define GCC_UNIPHY1_PORT5_RX_CLK 214224#define GCC_UNIPHY1_PORT5_TX_CLK 215225#define GCC_UNIPHY2_PORT6_RX_CLK 216226#define GCC_UNIPHY2_PORT6_TX_CLK 217227#define GCC_CRYPTO_AHB_CLK 218228#define GCC_CRYPTO_AXI_CLK 219229#define GCC_CRYPTO_CLK 220230#define GCC_GP1_CLK 221231#define GCC_GP2_CLK 222232#define GCC_GP3_CLK 223233#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224234#define GCC_PCIE0_RCHNG_CLK_SRC 225235#define GCC_PCIE0_RCHNG_CLK 226236#define GCC_CRYPTO_PPE_CLK 227237 238#define GCC_BLSP1_BCR 0239#define GCC_BLSP1_QUP1_BCR 1240#define GCC_BLSP1_UART1_BCR 2241#define GCC_BLSP1_QUP2_BCR 3242#define GCC_BLSP1_UART2_BCR 4243#define GCC_BLSP1_QUP3_BCR 5244#define GCC_BLSP1_UART3_BCR 6245#define GCC_BLSP1_QUP4_BCR 7246#define GCC_BLSP1_UART4_BCR 8247#define GCC_BLSP1_QUP5_BCR 9248#define GCC_BLSP1_UART5_BCR 10249#define GCC_BLSP1_QUP6_BCR 11250#define GCC_BLSP1_UART6_BCR 12251#define GCC_IMEM_BCR 13252#define GCC_SMMU_BCR 14253#define GCC_APSS_TCU_BCR 15254#define GCC_SMMU_XPU_BCR 16255#define GCC_PCNOC_TBU_BCR 17256#define GCC_SMMU_CFG_BCR 18257#define GCC_PRNG_BCR 19258#define GCC_BOOT_ROM_BCR 20259#define GCC_CRYPTO_BCR 21260#define GCC_WCSS_BCR 22261#define GCC_WCSS_Q6_BCR 23262#define GCC_NSS_BCR 24263#define GCC_SEC_CTRL_BCR 25264#define GCC_ADSS_BCR 26265#define GCC_DDRSS_BCR 27266#define GCC_SYSTEM_NOC_BCR 28267#define GCC_PCNOC_BCR 29268#define GCC_TCSR_BCR 30269#define GCC_QDSS_BCR 31270#define GCC_DCD_BCR 32271#define GCC_MSG_RAM_BCR 33272#define GCC_MPM_BCR 34273#define GCC_SPMI_BCR 35274#define GCC_SPDM_BCR 36275#define GCC_RBCPR_BCR 37276#define GCC_RBCPR_MX_BCR 38277#define GCC_TLMM_BCR 39278#define GCC_RBCPR_WCSS_BCR 40279#define GCC_USB0_PHY_BCR 41280#define GCC_USB3PHY_0_PHY_BCR 42281#define GCC_USB0_BCR 43282#define GCC_USB1_PHY_BCR 44283#define GCC_USB3PHY_1_PHY_BCR 45284#define GCC_USB1_BCR 46285#define GCC_QUSB2_0_PHY_BCR 47286#define GCC_QUSB2_1_PHY_BCR 48287#define GCC_SDCC1_BCR 49288#define GCC_SDCC2_BCR 50289#define GCC_SNOC_BUS_TIMEOUT0_BCR 51290#define GCC_SNOC_BUS_TIMEOUT2_BCR 52291#define GCC_SNOC_BUS_TIMEOUT3_BCR 53292#define GCC_PCNOC_BUS_TIMEOUT0_BCR 54293#define GCC_PCNOC_BUS_TIMEOUT1_BCR 55294#define GCC_PCNOC_BUS_TIMEOUT2_BCR 56295#define GCC_PCNOC_BUS_TIMEOUT3_BCR 57296#define GCC_PCNOC_BUS_TIMEOUT4_BCR 58297#define GCC_PCNOC_BUS_TIMEOUT5_BCR 59298#define GCC_PCNOC_BUS_TIMEOUT6_BCR 60299#define GCC_PCNOC_BUS_TIMEOUT7_BCR 61300#define GCC_PCNOC_BUS_TIMEOUT8_BCR 62301#define GCC_PCNOC_BUS_TIMEOUT9_BCR 63302#define GCC_UNIPHY0_BCR 64303#define GCC_UNIPHY1_BCR 65304#define GCC_UNIPHY2_BCR 66305#define GCC_CMN_12GPLL_BCR 67306#define GCC_QPIC_BCR 68307#define GCC_MDIO_BCR 69308#define GCC_PCIE1_TBU_BCR 70309#define GCC_WCSS_CORE_TBU_BCR 71310#define GCC_WCSS_Q6_TBU_BCR 72311#define GCC_USB0_TBU_BCR 73312#define GCC_USB1_TBU_BCR 74313#define GCC_PCIE0_TBU_BCR 75314#define GCC_NSS_NOC_TBU_BCR 76315#define GCC_PCIE0_BCR 77316#define GCC_PCIE0_PHY_BCR 78317#define GCC_PCIE0PHY_PHY_BCR 79318#define GCC_PCIE0_LINK_DOWN_BCR 80319#define GCC_PCIE1_BCR 81320#define GCC_PCIE1_PHY_BCR 82321#define GCC_PCIE1PHY_PHY_BCR 83322#define GCC_PCIE1_LINK_DOWN_BCR 84323#define GCC_DCC_BCR 85324#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 86325#define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR 87326#define GCC_SMMU_CATS_BCR 88327#define GCC_UBI0_AXI_ARES 89328#define GCC_UBI0_AHB_ARES 90329#define GCC_UBI0_NC_AXI_ARES 91330#define GCC_UBI0_DBG_ARES 92331#define GCC_UBI0_CORE_CLAMP_ENABLE 93332#define GCC_UBI0_CLKRST_CLAMP_ENABLE 94333#define GCC_UBI1_AXI_ARES 95334#define GCC_UBI1_AHB_ARES 96335#define GCC_UBI1_NC_AXI_ARES 97336#define GCC_UBI1_DBG_ARES 98337#define GCC_UBI1_CORE_CLAMP_ENABLE 99338#define GCC_UBI1_CLKRST_CLAMP_ENABLE 100339#define GCC_NSS_CFG_ARES 101340#define GCC_NSS_IMEM_ARES 102341#define GCC_NSS_NOC_ARES 103342#define GCC_NSS_CRYPTO_ARES 104343#define GCC_NSS_CSR_ARES 105344#define GCC_NSS_CE_APB_ARES 106345#define GCC_NSS_CE_AXI_ARES 107346#define GCC_NSSNOC_CE_APB_ARES 108347#define GCC_NSSNOC_CE_AXI_ARES 109348#define GCC_NSSNOC_UBI0_AHB_ARES 110349#define GCC_NSSNOC_UBI1_AHB_ARES 111350#define GCC_NSSNOC_SNOC_ARES 112351#define GCC_NSSNOC_CRYPTO_ARES 113352#define GCC_NSSNOC_ATB_ARES 114353#define GCC_NSSNOC_QOSGEN_REF_ARES 115354#define GCC_NSSNOC_TIMEOUT_REF_ARES 116355#define GCC_PCIE0_PIPE_ARES 117356#define GCC_PCIE0_SLEEP_ARES 118357#define GCC_PCIE0_CORE_STICKY_ARES 119358#define GCC_PCIE0_AXI_MASTER_ARES 120359#define GCC_PCIE0_AXI_SLAVE_ARES 121360#define GCC_PCIE0_AHB_ARES 122361#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 123362#define GCC_PCIE1_PIPE_ARES 124363#define GCC_PCIE1_SLEEP_ARES 125364#define GCC_PCIE1_CORE_STICKY_ARES 126365#define GCC_PCIE1_AXI_MASTER_ARES 127366#define GCC_PCIE1_AXI_SLAVE_ARES 128367#define GCC_PCIE1_AHB_ARES 129368#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130369#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131370#define GCC_PPE_FULL_RESET 132371#define GCC_UNIPHY0_SOFT_RESET 133372#define GCC_UNIPHY0_XPCS_RESET 134373#define GCC_UNIPHY1_SOFT_RESET 135374#define GCC_UNIPHY1_XPCS_RESET 136375#define GCC_UNIPHY2_SOFT_RESET 137376#define GCC_UNIPHY2_XPCS_RESET 138377#define GCC_EDMA_HW_RESET 139378#define GCC_NSSPORT1_RESET 140379#define GCC_NSSPORT2_RESET 141380#define GCC_NSSPORT3_RESET 142381#define GCC_NSSPORT4_RESET 143382#define GCC_NSSPORT5_RESET 144383#define GCC_NSSPORT6_RESET 145384 385#define USB0_GDSC 0386#define USB1_GDSC 1387 388#endif389