105 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */2/*3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>4 */5 6#ifndef _DT_BINDINGS_CLK_MSM_GCC_9607_H7#define _DT_BINDINGS_CLK_MSM_GCC_9607_H8 9#define GPLL0 010#define GPLL0_EARLY 111#define GPLL1 212#define GPLL1_VOTE 313#define GPLL2 414#define GPLL2_EARLY 515#define PCNOC_BFDCD_CLK_SRC 616#define SYSTEM_NOC_BFDCD_CLK_SRC 717#define GCC_SMMU_CFG_CLK 818#define APSS_AHB_CLK_SRC 919#define GCC_QDSS_DAP_CLK 1020#define BLSP1_QUP1_I2C_APPS_CLK_SRC 1121#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1222#define BLSP1_QUP2_I2C_APPS_CLK_SRC 1323#define BLSP1_QUP2_SPI_APPS_CLK_SRC 1424#define BLSP1_QUP3_I2C_APPS_CLK_SRC 1525#define BLSP1_QUP3_SPI_APPS_CLK_SRC 1626#define BLSP1_QUP4_I2C_APPS_CLK_SRC 1727#define BLSP1_QUP4_SPI_APPS_CLK_SRC 1828#define BLSP1_QUP5_I2C_APPS_CLK_SRC 1929#define BLSP1_QUP5_SPI_APPS_CLK_SRC 2030#define BLSP1_QUP6_I2C_APPS_CLK_SRC 2131#define BLSP1_QUP6_SPI_APPS_CLK_SRC 2232#define BLSP1_UART1_APPS_CLK_SRC 2333#define BLSP1_UART2_APPS_CLK_SRC 2434#define CRYPTO_CLK_SRC 2535#define GP1_CLK_SRC 2636#define GP2_CLK_SRC 2737#define GP3_CLK_SRC 2838#define PDM2_CLK_SRC 2939#define SDCC1_APPS_CLK_SRC 3040#define SDCC2_APPS_CLK_SRC 3141#define APSS_TCU_CLK_SRC 3242#define USB_HS_SYSTEM_CLK_SRC 3343#define GCC_BLSP1_AHB_CLK 3444#define GCC_BLSP1_SLEEP_CLK 3545#define GCC_BLSP1_QUP1_I2C_APPS_CLK 3646#define GCC_BLSP1_QUP1_SPI_APPS_CLK 3747#define GCC_BLSP1_QUP2_I2C_APPS_CLK 3848#define GCC_BLSP1_QUP2_SPI_APPS_CLK 3949#define GCC_BLSP1_QUP3_I2C_APPS_CLK 4050#define GCC_BLSP1_QUP3_SPI_APPS_CLK 4151#define GCC_BLSP1_QUP4_I2C_APPS_CLK 4252#define GCC_BLSP1_QUP4_SPI_APPS_CLK 4353#define GCC_BLSP1_QUP5_I2C_APPS_CLK 4454#define GCC_BLSP1_QUP5_SPI_APPS_CLK 4555#define GCC_BLSP1_QUP6_I2C_APPS_CLK 4656#define GCC_BLSP1_QUP6_SPI_APPS_CLK 4757#define GCC_BLSP1_UART1_APPS_CLK 4858#define GCC_BLSP1_UART2_APPS_CLK 4959#define GCC_BOOT_ROM_AHB_CLK 5060#define GCC_CRYPTO_AHB_CLK 5161#define GCC_CRYPTO_AXI_CLK 5262#define GCC_CRYPTO_CLK 5363#define GCC_GP1_CLK 5464#define GCC_GP2_CLK 5565#define GCC_GP3_CLK 5666#define GCC_MSS_CFG_AHB_CLK 5767#define GCC_PDM2_CLK 5868#define GCC_PDM_AHB_CLK 5969#define GCC_PRNG_AHB_CLK 6070#define GCC_SDCC1_AHB_CLK 6171#define GCC_SDCC1_APPS_CLK 6272#define GCC_SDCC2_AHB_CLK 6373#define GCC_SDCC2_APPS_CLK 6474#define GCC_USB2A_PHY_SLEEP_CLK 6575#define GCC_USB_HS_AHB_CLK 6676#define GCC_USB_HS_SYSTEM_CLK 6777#define GCC_APSS_TCU_CLK 6878#define GCC_MSS_Q6_BIMC_AXI_CLK 6979#define BIMC_PLL 7080#define BIMC_PLL_VOTE 7181#define BIMC_DDR_CLK_SRC 7282#define BLSP1_UART3_APPS_CLK_SRC 7383#define BLSP1_UART4_APPS_CLK_SRC 7484#define BLSP1_UART5_APPS_CLK_SRC 7585#define BLSP1_UART6_APPS_CLK_SRC 7686#define GCC_BLSP1_UART3_APPS_CLK 7787#define GCC_BLSP1_UART4_APPS_CLK 7888#define GCC_BLSP1_UART5_APPS_CLK 7989#define GCC_BLSP1_UART6_APPS_CLK 8090#define GCC_APSS_AHB_CLK 8191#define GCC_APSS_AXI_CLK 8292#define GCC_USB_HS_PHY_CFG_AHB_CLK 8393#define GCC_USB_HSIC_CLK_SRC 8494#define GCC_USB_HSIC_IO_CAL_CLK_SRC 8595#define GCC_USB_HSIC_SYSTEM_CLK_SRC 8696 97/* Resets */98#define USB2_HS_PHY_ONLY_BCR 099#define QUSB2_PHY_BCR 1100#define GCC_MSS_RESTART 2101#define USB_HS_HSIC_BCR 3102#define USB_HS_BCR 4103 104#endif105