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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (C) 2022 Kernkonzept GmbH.4 */5 6#ifndef _DT_BINDINGS_CLK_QCOM_GCC_8909_H7#define _DT_BINDINGS_CLK_QCOM_GCC_8909_H8 9/* PLLs */10#define GPLL0_EARLY 011#define GPLL0 112#define GPLL1 213#define GPLL1_VOTE 314#define GPLL2_EARLY 415#define GPLL2 516#define BIMC_PLL_EARLY 617#define BIMC_PLL 718 19/* RCGs */20#define APSS_AHB_CLK_SRC 821#define BIMC_DDR_CLK_SRC 922#define BIMC_GPU_CLK_SRC 1023#define BLSP1_QUP1_I2C_APPS_CLK_SRC 1124#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1225#define BLSP1_QUP2_I2C_APPS_CLK_SRC 1326#define BLSP1_QUP2_SPI_APPS_CLK_SRC 1427#define BLSP1_QUP3_I2C_APPS_CLK_SRC 1528#define BLSP1_QUP3_SPI_APPS_CLK_SRC 1629#define BLSP1_QUP4_I2C_APPS_CLK_SRC 1730#define BLSP1_QUP4_SPI_APPS_CLK_SRC 1831#define BLSP1_QUP5_I2C_APPS_CLK_SRC 1932#define BLSP1_QUP5_SPI_APPS_CLK_SRC 2033#define BLSP1_QUP6_I2C_APPS_CLK_SRC 2134#define BLSP1_QUP6_SPI_APPS_CLK_SRC 2235#define BLSP1_UART1_APPS_CLK_SRC 2336#define BLSP1_UART2_APPS_CLK_SRC 2437#define BYTE0_CLK_SRC 2538#define CAMSS_GP0_CLK_SRC 2639#define CAMSS_GP1_CLK_SRC 2740#define CAMSS_TOP_AHB_CLK_SRC 2841#define CODEC_DIGCODEC_CLK_SRC 2942#define CRYPTO_CLK_SRC 3043#define CSI0_CLK_SRC 3144#define CSI0PHYTIMER_CLK_SRC 3245#define CSI1_CLK_SRC 3346#define ESC0_CLK_SRC 3447#define GFX3D_CLK_SRC 3548#define GP1_CLK_SRC 3649#define GP2_CLK_SRC 3750#define GP3_CLK_SRC 3851#define MCLK0_CLK_SRC 3952#define MCLK1_CLK_SRC 4053#define MDP_CLK_SRC 4154#define PCLK0_CLK_SRC 4255#define PCNOC_BFDCD_CLK_SRC 4356#define PDM2_CLK_SRC 4457#define SDCC1_APPS_CLK_SRC 4558#define SDCC2_APPS_CLK_SRC 4659#define SYSTEM_NOC_BFDCD_CLK_SRC 4760#define ULTAUDIO_AHBFABRIC_CLK_SRC 4861#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 4962#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 5063#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 5164#define ULTAUDIO_XO_CLK_SRC 5265#define USB_HS_SYSTEM_CLK_SRC 5366#define VCODEC0_CLK_SRC 5467#define VFE0_CLK_SRC 5568#define VSYNC_CLK_SRC 5669 70/* Voteable Clocks */71#define GCC_APSS_TCU_CLK 5772#define GCC_BLSP1_AHB_CLK 5873#define GCC_BLSP1_SLEEP_CLK 5974#define GCC_BOOT_ROM_AHB_CLK 6075#define GCC_CRYPTO_CLK 6176#define GCC_CRYPTO_AHB_CLK 6277#define GCC_CRYPTO_AXI_CLK 6378#define GCC_GFX_TBU_CLK 6479#define GCC_GFX_TCU_CLK 6580#define GCC_GTCU_AHB_CLK 6681#define GCC_MDP_TBU_CLK 6782#define GCC_PRNG_AHB_CLK 6883#define GCC_SMMU_CFG_CLK 6984#define GCC_VENUS_TBU_CLK 7085#define GCC_VFE_TBU_CLK 7186 87/* Branches */88#define GCC_BIMC_GFX_CLK 7289#define GCC_BIMC_GPU_CLK 7390#define GCC_BLSP1_QUP1_I2C_APPS_CLK 7491#define GCC_BLSP1_QUP1_SPI_APPS_CLK 7592#define GCC_BLSP1_QUP2_I2C_APPS_CLK 7693#define GCC_BLSP1_QUP2_SPI_APPS_CLK 7794#define GCC_BLSP1_QUP3_I2C_APPS_CLK 7895#define GCC_BLSP1_QUP3_SPI_APPS_CLK 7996#define GCC_BLSP1_QUP4_I2C_APPS_CLK 8097#define GCC_BLSP1_QUP4_SPI_APPS_CLK 8198#define GCC_BLSP1_QUP5_I2C_APPS_CLK 8299#define GCC_BLSP1_QUP5_SPI_APPS_CLK 83100#define GCC_BLSP1_QUP6_I2C_APPS_CLK 84101#define GCC_BLSP1_QUP6_SPI_APPS_CLK 85102#define GCC_BLSP1_UART1_APPS_CLK 86103#define GCC_BLSP1_UART2_APPS_CLK 87104#define GCC_CAMSS_AHB_CLK 88105#define GCC_CAMSS_CSI0_CLK 89106#define GCC_CAMSS_CSI0_AHB_CLK 90107#define GCC_CAMSS_CSI0PHY_CLK 91108#define GCC_CAMSS_CSI0PHYTIMER_CLK 92109#define GCC_CAMSS_CSI0PIX_CLK 93110#define GCC_CAMSS_CSI0RDI_CLK 94111#define GCC_CAMSS_CSI1_CLK 95112#define GCC_CAMSS_CSI1_AHB_CLK 96113#define GCC_CAMSS_CSI1PHY_CLK 97114#define GCC_CAMSS_CSI1PIX_CLK 98115#define GCC_CAMSS_CSI1RDI_CLK 99116#define GCC_CAMSS_CSI_VFE0_CLK 100117#define GCC_CAMSS_GP0_CLK 101118#define GCC_CAMSS_GP1_CLK 102119#define GCC_CAMSS_ISPIF_AHB_CLK 103120#define GCC_CAMSS_MCLK0_CLK 104121#define GCC_CAMSS_MCLK1_CLK 105122#define GCC_CAMSS_TOP_AHB_CLK 106123#define GCC_CAMSS_VFE0_CLK 107124#define GCC_CAMSS_VFE_AHB_CLK 108125#define GCC_CAMSS_VFE_AXI_CLK 109126#define GCC_CODEC_DIGCODEC_CLK 110127#define GCC_GP1_CLK 111128#define GCC_GP2_CLK 112129#define GCC_GP3_CLK 113130#define GCC_MDSS_AHB_CLK 114131#define GCC_MDSS_AXI_CLK 115132#define GCC_MDSS_BYTE0_CLK 116133#define GCC_MDSS_ESC0_CLK 117134#define GCC_MDSS_MDP_CLK 118135#define GCC_MDSS_PCLK0_CLK 119136#define GCC_MDSS_VSYNC_CLK 120137#define GCC_MSS_CFG_AHB_CLK 121138#define GCC_MSS_Q6_BIMC_AXI_CLK 122139#define GCC_OXILI_AHB_CLK 123140#define GCC_OXILI_GFX3D_CLK 124141#define GCC_PDM2_CLK 125142#define GCC_PDM_AHB_CLK 126143#define GCC_SDCC1_AHB_CLK 127144#define GCC_SDCC1_APPS_CLK 128145#define GCC_SDCC2_AHB_CLK 129146#define GCC_SDCC2_APPS_CLK 130147#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 131148#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 132149#define GCC_ULTAUDIO_AVSYNC_XO_CLK 133150#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 134151#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 135152#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 136153#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 137154#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 138155#define GCC_ULTAUDIO_STC_XO_CLK 139156#define GCC_USB2A_PHY_SLEEP_CLK 140157#define GCC_USB_HS_AHB_CLK 141158#define GCC_USB_HS_PHY_CFG_AHB_CLK 142159#define GCC_USB_HS_SYSTEM_CLK 143160#define GCC_VENUS0_AHB_CLK 144161#define GCC_VENUS0_AXI_CLK 145162#define GCC_VENUS0_CORE0_VCODEC0_CLK 146163#define GCC_VENUS0_VCODEC0_CLK 147164 165/* Resets */166#define GCC_AUDIO_CORE_BCR 0167#define GCC_BLSP1_BCR 1168#define GCC_BLSP1_QUP1_BCR 2169#define GCC_BLSP1_QUP2_BCR 3170#define GCC_BLSP1_QUP3_BCR 4171#define GCC_BLSP1_QUP4_BCR 5172#define GCC_BLSP1_QUP5_BCR 6173#define GCC_BLSP1_QUP6_BCR 7174#define GCC_BLSP1_UART1_BCR 8175#define GCC_BLSP1_UART2_BCR 9176#define GCC_CAMSS_CSI0_BCR 10177#define GCC_CAMSS_CSI0PHY_BCR 11178#define GCC_CAMSS_CSI0PIX_BCR 12179#define GCC_CAMSS_CSI0RDI_BCR 13180#define GCC_CAMSS_CSI1_BCR 14181#define GCC_CAMSS_CSI1PHY_BCR 15182#define GCC_CAMSS_CSI1PIX_BCR 16183#define GCC_CAMSS_CSI1RDI_BCR 17184#define GCC_CAMSS_CSI_VFE0_BCR 18185#define GCC_CAMSS_GP0_BCR 19186#define GCC_CAMSS_GP1_BCR 20187#define GCC_CAMSS_ISPIF_BCR 21188#define GCC_CAMSS_MCLK0_BCR 22189#define GCC_CAMSS_MCLK1_BCR 23190#define GCC_CAMSS_PHY0_BCR 24191#define GCC_CAMSS_TOP_BCR 25192#define GCC_CAMSS_TOP_AHB_BCR 26193#define GCC_CAMSS_VFE_BCR 27194#define GCC_CRYPTO_BCR 28195#define GCC_MDSS_BCR 29196#define GCC_OXILI_BCR 30197#define GCC_PDM_BCR 31198#define GCC_PRNG_BCR 32199#define GCC_QUSB2_PHY_BCR 33200#define GCC_SDCC1_BCR 34201#define GCC_SDCC2_BCR 35202#define GCC_ULT_AUDIO_BCR 36203#define GCC_USB2A_PHY_BCR 37204#define GCC_USB2_HS_PHY_ONLY_BCR 38205#define GCC_USB_HS_BCR 39206#define GCC_VENUS0_BCR 40207 208/* Subsystem Restart */209#define GCC_MSS_RESTART 41210 211/* Power Domains */212#define MDSS_GDSC 0213#define OXILI_GDSC 1214#define VENUS_GDSC 2215#define VENUS_CORE0_GDSC 3216#define VFE_GDSC 4217 218#endif219