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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (C) 2016, The Linux Foundation. All rights reserved.4 * Copyright (C) 2016-2021, AngeloGioacchino Del Regno5 * <angelogioacchino.delregno@somainline.org>6 */7 8#ifndef _DT_BINDINGS_CLK_MSM_GCC_8976_H9#define _DT_BINDINGS_CLK_MSM_GCC_8976_H10 11#define GPLL0 012#define GPLL2 113#define GPLL3 214#define GPLL4 315#define GPLL6 416#define GPLL0_CLK_SRC 517#define GPLL2_CLK_SRC 618#define GPLL3_CLK_SRC 719#define GPLL4_CLK_SRC 820#define GPLL6_CLK_SRC 921#define GCC_BLSP1_QUP1_SPI_APPS_CLK 1022#define GCC_BLSP1_QUP1_I2C_APPS_CLK 1123#define GCC_BLSP1_QUP2_I2C_APPS_CLK 1224#define GCC_BLSP1_QUP2_SPI_APPS_CLK 1325#define GCC_BLSP1_QUP3_I2C_APPS_CLK 1426#define GCC_BLSP1_QUP3_SPI_APPS_CLK 1527#define GCC_BLSP1_QUP4_I2C_APPS_CLK 1628#define GCC_BLSP1_QUP4_SPI_APPS_CLK 1729#define GCC_BLSP1_UART1_APPS_CLK 1830#define GCC_BLSP1_UART2_APPS_CLK 1931#define GCC_BLSP2_QUP1_I2C_APPS_CLK 2032#define GCC_BLSP2_QUP1_SPI_APPS_CLK 2133#define GCC_BLSP2_QUP2_I2C_APPS_CLK 2234#define GCC_BLSP2_QUP2_SPI_APPS_CLK 2335#define GCC_BLSP2_QUP3_I2C_APPS_CLK 2436#define GCC_BLSP2_QUP3_SPI_APPS_CLK 2537#define GCC_BLSP2_QUP4_I2C_APPS_CLK 2638#define GCC_BLSP2_QUP4_SPI_APPS_CLK 2739#define GCC_BLSP2_UART1_APPS_CLK 2840#define GCC_BLSP2_UART2_APPS_CLK 2941#define GCC_CAMSS_CCI_AHB_CLK 3042#define GCC_CAMSS_CCI_CLK 3143#define GCC_CAMSS_CPP_AHB_CLK 3244#define GCC_CAMSS_CPP_AXI_CLK 3345#define GCC_CAMSS_CPP_CLK 3446#define GCC_CAMSS_CSI0_AHB_CLK 3547#define GCC_CAMSS_CSI0_CLK 3648#define GCC_CAMSS_CSI0PHY_CLK 3749#define GCC_CAMSS_CSI0PIX_CLK 3850#define GCC_CAMSS_CSI0RDI_CLK 3951#define GCC_CAMSS_CSI1_AHB_CLK 4052#define GCC_CAMSS_CSI1_CLK 4153#define GCC_CAMSS_CSI1PHY_CLK 4254#define GCC_CAMSS_CSI1PIX_CLK 4355#define GCC_CAMSS_CSI1RDI_CLK 4456#define GCC_CAMSS_CSI2_AHB_CLK 4557#define GCC_CAMSS_CSI2_CLK 4658#define GCC_CAMSS_CSI2PHY_CLK 4759#define GCC_CAMSS_CSI2PIX_CLK 4860#define GCC_CAMSS_CSI2RDI_CLK 4961#define GCC_CAMSS_CSI_VFE0_CLK 5062#define GCC_CAMSS_CSI_VFE1_CLK 5163#define GCC_CAMSS_GP0_CLK 5264#define GCC_CAMSS_GP1_CLK 5365#define GCC_CAMSS_ISPIF_AHB_CLK 5466#define GCC_CAMSS_JPEG0_CLK 5567#define GCC_CAMSS_JPEG_AHB_CLK 5668#define GCC_CAMSS_JPEG_AXI_CLK 5769#define GCC_CAMSS_MCLK0_CLK 5870#define GCC_CAMSS_MCLK1_CLK 5971#define GCC_CAMSS_MCLK2_CLK 6072#define GCC_CAMSS_MICRO_AHB_CLK 6173#define GCC_CAMSS_CSI0PHYTIMER_CLK 6274#define GCC_CAMSS_CSI1PHYTIMER_CLK 6375#define GCC_CAMSS_AHB_CLK 6476#define GCC_CAMSS_TOP_AHB_CLK 6577#define GCC_CAMSS_VFE0_CLK 6678#define GCC_CAMSS_VFE_AHB_CLK 6779#define GCC_CAMSS_VFE_AXI_CLK 6880#define GCC_CAMSS_VFE1_AHB_CLK 6981#define GCC_CAMSS_VFE1_AXI_CLK 7082#define GCC_CAMSS_VFE1_CLK 7183#define GCC_DCC_CLK 7284#define GCC_GP1_CLK 7385#define GCC_GP2_CLK 7486#define GCC_GP3_CLK 7587#define GCC_MDSS_AHB_CLK 7688#define GCC_MDSS_AXI_CLK 7789#define GCC_MDSS_ESC0_CLK 7890#define GCC_MDSS_ESC1_CLK 7991#define GCC_MDSS_MDP_CLK 8092#define GCC_MDSS_VSYNC_CLK 8193#define GCC_MSS_CFG_AHB_CLK 8294#define GCC_MSS_Q6_BIMC_AXI_CLK 8395#define GCC_PDM2_CLK 8496#define GCC_PRNG_AHB_CLK 8597#define GCC_PDM_AHB_CLK 8698#define GCC_RBCPR_GFX_AHB_CLK 8799#define GCC_RBCPR_GFX_CLK 88100#define GCC_SDCC1_AHB_CLK 89101#define GCC_SDCC1_APPS_CLK 90102#define GCC_SDCC1_ICE_CORE_CLK 91103#define GCC_SDCC2_AHB_CLK 92104#define GCC_SDCC2_APPS_CLK 93105#define GCC_SDCC3_AHB_CLK 94106#define GCC_SDCC3_APPS_CLK 95107#define GCC_USB2A_PHY_SLEEP_CLK 96108#define GCC_USB_HS_PHY_CFG_AHB_CLK 97109#define GCC_USB_FS_AHB_CLK 98110#define GCC_USB_FS_IC_CLK 99111#define GCC_USB_FS_SYSTEM_CLK 100112#define GCC_USB_HS_AHB_CLK 101113#define GCC_USB_HS_SYSTEM_CLK 102114#define GCC_VENUS0_AHB_CLK 103115#define GCC_VENUS0_AXI_CLK 104116#define GCC_VENUS0_CORE0_VCODEC0_CLK 105117#define GCC_VENUS0_CORE1_VCODEC0_CLK 106118#define GCC_VENUS0_VCODEC0_CLK 107119#define GCC_APSS_AHB_CLK 108120#define GCC_APSS_AXI_CLK 109121#define GCC_BLSP1_AHB_CLK 110122#define GCC_BLSP2_AHB_CLK 111123#define GCC_BOOT_ROM_AHB_CLK 112124#define GCC_CRYPTO_AHB_CLK 113125#define GCC_CRYPTO_AXI_CLK 114126#define GCC_CRYPTO_CLK 115127#define GCC_CPP_TBU_CLK 116128#define GCC_APSS_TCU_CLK 117129#define GCC_JPEG_TBU_CLK 118130#define GCC_MDP_RT_TBU_CLK 119131#define GCC_MDP_TBU_CLK 120132#define GCC_SMMU_CFG_CLK 121133#define GCC_VENUS_1_TBU_CLK 122134#define GCC_VENUS_TBU_CLK 123135#define GCC_VFE1_TBU_CLK 124136#define GCC_VFE_TBU_CLK 125137#define GCC_APS_0_CLK 126138#define GCC_APS_1_CLK 127139#define APS_0_CLK_SRC 128140#define APS_1_CLK_SRC 129141#define APSS_AHB_CLK_SRC 130142#define BLSP1_QUP1_I2C_APPS_CLK_SRC 131143#define BLSP1_QUP1_SPI_APPS_CLK_SRC 132144#define BLSP1_QUP2_I2C_APPS_CLK_SRC 133145#define BLSP1_QUP2_SPI_APPS_CLK_SRC 134146#define BLSP1_QUP3_I2C_APPS_CLK_SRC 135147#define BLSP1_QUP3_SPI_APPS_CLK_SRC 136148#define BLSP1_QUP4_I2C_APPS_CLK_SRC 137149#define BLSP1_QUP4_SPI_APPS_CLK_SRC 138150#define BLSP1_UART1_APPS_CLK_SRC 139151#define BLSP1_UART2_APPS_CLK_SRC 140152#define BLSP2_QUP1_I2C_APPS_CLK_SRC 141153#define BLSP2_QUP1_SPI_APPS_CLK_SRC 142154#define BLSP2_QUP2_I2C_APPS_CLK_SRC 143155#define BLSP2_QUP2_SPI_APPS_CLK_SRC 144156#define BLSP2_QUP3_I2C_APPS_CLK_SRC 145157#define BLSP2_QUP3_SPI_APPS_CLK_SRC 146158#define BLSP2_QUP4_I2C_APPS_CLK_SRC 147159#define BLSP2_QUP4_SPI_APPS_CLK_SRC 148160#define BLSP2_UART1_APPS_CLK_SRC 149161#define BLSP2_UART2_APPS_CLK_SRC 150162#define CCI_CLK_SRC 151163#define CPP_CLK_SRC 152164#define CSI0_CLK_SRC 153165#define CSI1_CLK_SRC 154166#define CSI2_CLK_SRC 155167#define CAMSS_GP0_CLK_SRC 156168#define CAMSS_GP1_CLK_SRC 157169#define JPEG0_CLK_SRC 158170#define MCLK0_CLK_SRC 159171#define MCLK1_CLK_SRC 160172#define MCLK2_CLK_SRC 161173#define CSI0PHYTIMER_CLK_SRC 162174#define CSI1PHYTIMER_CLK_SRC 163175#define CAMSS_TOP_AHB_CLK_SRC 164176#define VFE0_CLK_SRC 165177#define VFE1_CLK_SRC 166178#define CRYPTO_CLK_SRC 167179#define GP1_CLK_SRC 168180#define GP2_CLK_SRC 169181#define GP3_CLK_SRC 170182#define ESC0_CLK_SRC 171183#define ESC1_CLK_SRC 172184#define MDP_CLK_SRC 173185#define VSYNC_CLK_SRC 174186#define PDM2_CLK_SRC 175187#define RBCPR_GFX_CLK_SRC 176188#define SDCC1_APPS_CLK_SRC 177189#define SDCC1_ICE_CORE_CLK_SRC 178190#define SDCC2_APPS_CLK_SRC 179191#define SDCC3_APPS_CLK_SRC 180192#define USB_FS_IC_CLK_SRC 181193#define USB_FS_SYSTEM_CLK_SRC 182194#define USB_HS_SYSTEM_CLK_SRC 183195#define VCODEC0_CLK_SRC 184196#define GCC_MDSS_BYTE0_CLK_SRC 185197#define GCC_MDSS_BYTE1_CLK_SRC 186198#define GCC_MDSS_BYTE0_CLK 187199#define GCC_MDSS_BYTE1_CLK 188200#define GCC_MDSS_PCLK0_CLK_SRC 189201#define GCC_MDSS_PCLK1_CLK_SRC 190202#define GCC_MDSS_PCLK0_CLK 191203#define GCC_MDSS_PCLK1_CLK 192204#define GCC_GFX3D_CLK_SRC 193205#define GCC_GFX3D_OXILI_CLK 194206#define GCC_GFX3D_BIMC_CLK 195207#define GCC_GFX3D_OXILI_AHB_CLK 196208#define GCC_GFX3D_OXILI_AON_CLK 197209#define GCC_GFX3D_OXILI_GMEM_CLK 198210#define GCC_GFX3D_OXILI_TIMER_CLK 199211#define GCC_GFX3D_TBU0_CLK 200212#define GCC_GFX3D_TBU1_CLK 201213#define GCC_GFX3D_TCU_CLK 202214#define GCC_GFX3D_GTCU_AHB_CLK 203215 216/* GCC block resets */217#define RST_CAMSS_MICRO_BCR 0218#define RST_USB_HS_BCR 1219#define RST_QUSB2_PHY_BCR 2220#define RST_USB2_HS_PHY_ONLY_BCR 3221#define RST_USB_HS_PHY_CFG_AHB_BCR 4222#define RST_USB_FS_BCR 5223#define RST_CAMSS_CSI1PIX_BCR 6224#define RST_CAMSS_CSI_VFE1_BCR 7225#define RST_CAMSS_VFE1_BCR 8226#define RST_CAMSS_CPP_BCR 9227#define RST_MSS_BCR 10228 229/* GDSCs */230#define VENUS_GDSC 0231#define VENUS_CORE0_GDSC 1232#define VENUS_CORE1_GDSC 2233#define MDSS_GDSC 3234#define JPEG_GDSC 4235#define VFE0_GDSC 5236#define VFE1_GDSC 6237#define CPP_GDSC 7238#define OXILI_GX_GDSC 8239#define OXILI_CX_GDSC 9240 241#endif /* _DT_BINDINGS_CLK_MSM_GCC_8976_H */242