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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2016, The Linux Foundation. All rights reserved.4 */5 6#ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H7#define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H8 9#define BLSP1_QUP1_I2C_APPS_CLK_SRC 010#define BLSP1_QUP1_SPI_APPS_CLK_SRC 111#define BLSP1_QUP2_I2C_APPS_CLK_SRC 212#define BLSP1_QUP2_SPI_APPS_CLK_SRC 313#define BLSP1_QUP3_I2C_APPS_CLK_SRC 414#define BLSP1_QUP3_SPI_APPS_CLK_SRC 515#define BLSP1_QUP4_I2C_APPS_CLK_SRC 616#define BLSP1_QUP4_SPI_APPS_CLK_SRC 717#define BLSP1_QUP5_I2C_APPS_CLK_SRC 818#define BLSP1_QUP5_SPI_APPS_CLK_SRC 919#define BLSP1_QUP6_I2C_APPS_CLK_SRC 1020#define BLSP1_QUP6_SPI_APPS_CLK_SRC 1121#define BLSP1_UART1_APPS_CLK_SRC 1222#define BLSP1_UART2_APPS_CLK_SRC 1323#define BLSP1_UART3_APPS_CLK_SRC 1424#define BLSP2_QUP1_I2C_APPS_CLK_SRC 1525#define BLSP2_QUP1_SPI_APPS_CLK_SRC 1626#define BLSP2_QUP2_I2C_APPS_CLK_SRC 1727#define BLSP2_QUP2_SPI_APPS_CLK_SRC 1828#define BLSP2_QUP3_I2C_APPS_CLK_SRC 1929#define BLSP2_QUP3_SPI_APPS_CLK_SRC 2030#define BLSP2_QUP4_I2C_APPS_CLK_SRC 2131#define BLSP2_QUP4_SPI_APPS_CLK_SRC 2232#define BLSP2_QUP5_I2C_APPS_CLK_SRC 2333#define BLSP2_QUP5_SPI_APPS_CLK_SRC 2434#define BLSP2_QUP6_I2C_APPS_CLK_SRC 2535#define BLSP2_QUP6_SPI_APPS_CLK_SRC 2636#define BLSP2_UART1_APPS_CLK_SRC 2737#define BLSP2_UART2_APPS_CLK_SRC 2838#define BLSP2_UART3_APPS_CLK_SRC 2939#define GCC_AGGRE1_NOC_XO_CLK 3040#define GCC_AGGRE1_UFS_AXI_CLK 3141#define GCC_AGGRE1_USB3_AXI_CLK 3242#define GCC_APSS_QDSS_TSCTR_DIV2_CLK 3343#define GCC_APSS_QDSS_TSCTR_DIV8_CLK 3444#define GCC_BIMC_HMSS_AXI_CLK 3545#define GCC_BIMC_MSS_Q6_AXI_CLK 3646#define GCC_BLSP1_AHB_CLK 3747#define GCC_BLSP1_QUP1_I2C_APPS_CLK 3848#define GCC_BLSP1_QUP1_SPI_APPS_CLK 3949#define GCC_BLSP1_QUP2_I2C_APPS_CLK 4050#define GCC_BLSP1_QUP2_SPI_APPS_CLK 4151#define GCC_BLSP1_QUP3_I2C_APPS_CLK 4252#define GCC_BLSP1_QUP3_SPI_APPS_CLK 4353#define GCC_BLSP1_QUP4_I2C_APPS_CLK 4454#define GCC_BLSP1_QUP4_SPI_APPS_CLK 4555#define GCC_BLSP1_QUP5_I2C_APPS_CLK 4656#define GCC_BLSP1_QUP5_SPI_APPS_CLK 4757#define GCC_BLSP1_QUP6_I2C_APPS_CLK 4858#define GCC_BLSP1_QUP6_SPI_APPS_CLK 4959#define GCC_BLSP1_SLEEP_CLK 5060#define GCC_BLSP1_UART1_APPS_CLK 5161#define GCC_BLSP1_UART2_APPS_CLK 5262#define GCC_BLSP1_UART3_APPS_CLK 5363#define GCC_BLSP2_AHB_CLK 5464#define GCC_BLSP2_QUP1_I2C_APPS_CLK 5565#define GCC_BLSP2_QUP1_SPI_APPS_CLK 5666#define GCC_BLSP2_QUP2_I2C_APPS_CLK 5767#define GCC_BLSP2_QUP2_SPI_APPS_CLK 5868#define GCC_BLSP2_QUP3_I2C_APPS_CLK 5969#define GCC_BLSP2_QUP3_SPI_APPS_CLK 6070#define GCC_BLSP2_QUP4_I2C_APPS_CLK 6171#define GCC_BLSP2_QUP4_SPI_APPS_CLK 6272#define GCC_BLSP2_QUP5_I2C_APPS_CLK 6373#define GCC_BLSP2_QUP5_SPI_APPS_CLK 6474#define GCC_BLSP2_QUP6_I2C_APPS_CLK 6575#define GCC_BLSP2_QUP6_SPI_APPS_CLK 6676#define GCC_BLSP2_SLEEP_CLK 6777#define GCC_BLSP2_UART1_APPS_CLK 6878#define GCC_BLSP2_UART2_APPS_CLK 6979#define GCC_BLSP2_UART3_APPS_CLK 7080#define GCC_CFG_NOC_USB3_AXI_CLK 7181#define GCC_GP1_CLK 7282#define GCC_GP2_CLK 7383#define GCC_GP3_CLK 7484#define GCC_GPU_BIMC_GFX_CLK 7585#define GCC_GPU_BIMC_GFX_SRC_CLK 7686#define GCC_GPU_CFG_AHB_CLK 7787#define GCC_GPU_SNOC_DVM_GFX_CLK 7888#define GCC_HMSS_AHB_CLK 7989#define GCC_HMSS_AT_CLK 8090#define GCC_HMSS_DVM_BUS_CLK 8191#define GCC_HMSS_RBCPR_CLK 8292#define GCC_HMSS_TRIG_CLK 8393#define GCC_LPASS_AT_CLK 8494#define GCC_LPASS_TRIG_CLK 8595#define GCC_MMSS_NOC_CFG_AHB_CLK 8696#define GCC_MMSS_QM_AHB_CLK 8797#define GCC_MMSS_QM_CORE_CLK 8898#define GCC_MMSS_SYS_NOC_AXI_CLK 8999#define GCC_MSS_AT_CLK 90100#define GCC_PCIE_0_AUX_CLK 91101#define GCC_PCIE_0_CFG_AHB_CLK 92102#define GCC_PCIE_0_MSTR_AXI_CLK 93103#define GCC_PCIE_0_PIPE_CLK 94104#define GCC_PCIE_0_SLV_AXI_CLK 95105#define GCC_PCIE_PHY_AUX_CLK 96106#define GCC_PDM2_CLK 97107#define GCC_PDM_AHB_CLK 98108#define GCC_PDM_XO4_CLK 99109#define GCC_PRNG_AHB_CLK 100110#define GCC_SDCC2_AHB_CLK 101111#define GCC_SDCC2_APPS_CLK 102112#define GCC_SDCC4_AHB_CLK 103113#define GCC_SDCC4_APPS_CLK 104114#define GCC_TSIF_AHB_CLK 105115#define GCC_TSIF_INACTIVITY_TIMERS_CLK 106116#define GCC_TSIF_REF_CLK 107117#define GCC_UFS_AHB_CLK 108118#define GCC_UFS_AXI_CLK 109119#define GCC_UFS_ICE_CORE_CLK 110120#define GCC_UFS_PHY_AUX_CLK 111121#define GCC_UFS_RX_SYMBOL_0_CLK 112122#define GCC_UFS_RX_SYMBOL_1_CLK 113123#define GCC_UFS_TX_SYMBOL_0_CLK 114124#define GCC_UFS_UNIPRO_CORE_CLK 115125#define GCC_USB30_MASTER_CLK 116126#define GCC_USB30_MOCK_UTMI_CLK 117127#define GCC_USB30_SLEEP_CLK 118128#define GCC_USB3_PHY_AUX_CLK 119129#define GCC_USB3_PHY_PIPE_CLK 120130#define GCC_USB_PHY_CFG_AHB2PHY_CLK 121131#define GP1_CLK_SRC 122132#define GP2_CLK_SRC 123133#define GP3_CLK_SRC 124134#define GPLL0 125135#define GPLL0_OUT_EVEN 126136#define GPLL0_OUT_MAIN 127137#define GPLL0_OUT_ODD 128138#define GPLL0_OUT_TEST 129139#define GPLL1 130140#define GPLL1_OUT_EVEN 131141#define GPLL1_OUT_MAIN 132142#define GPLL1_OUT_ODD 133143#define GPLL1_OUT_TEST 134144#define GPLL2 135145#define GPLL2_OUT_EVEN 136146#define GPLL2_OUT_MAIN 137147#define GPLL2_OUT_ODD 138148#define GPLL2_OUT_TEST 139149#define GPLL3 140150#define GPLL3_OUT_EVEN 141151#define GPLL3_OUT_MAIN 142152#define GPLL3_OUT_ODD 143153#define GPLL3_OUT_TEST 144154#define GPLL4 145155#define GPLL4_OUT_EVEN 146156#define GPLL4_OUT_MAIN 147157#define GPLL4_OUT_ODD 148158#define GPLL4_OUT_TEST 149159#define GPLL6 150160#define GPLL6_OUT_EVEN 151161#define GPLL6_OUT_MAIN 152162#define GPLL6_OUT_ODD 153163#define GPLL6_OUT_TEST 154164#define HMSS_AHB_CLK_SRC 155165#define HMSS_RBCPR_CLK_SRC 156166#define PCIE_AUX_CLK_SRC 157167#define PDM2_CLK_SRC 158168#define SDCC2_APPS_CLK_SRC 159169#define SDCC4_APPS_CLK_SRC 160170#define TSIF_REF_CLK_SRC 161171#define UFS_AXI_CLK_SRC 162172#define USB30_MASTER_CLK_SRC 163173#define USB30_MOCK_UTMI_CLK_SRC 164174#define USB3_PHY_AUX_CLK_SRC 165175#define GCC_USB3_CLKREF_CLK 166176#define GCC_HDMI_CLKREF_CLK 167177#define GCC_UFS_CLKREF_CLK 168178#define GCC_PCIE_CLKREF_CLK 169179#define GCC_RX1_USB2_CLKREF_CLK 170180#define GCC_MSS_CFG_AHB_CLK 171181#define GCC_BOOT_ROM_AHB_CLK 172182#define GCC_MSS_GPLL0_DIV_CLK_SRC 173183#define GCC_MSS_SNOC_AXI_CLK 174184#define GCC_MSS_MNOC_BIMC_AXI_CLK 175185#define GCC_BIMC_GFX_CLK 176186#define UFS_UNIPRO_CORE_CLK_SRC 177187#define GCC_MMSS_GPLL0_CLK 178188#define HMSS_GPLL0_CLK_SRC 179189#define GCC_IM_SLEEP 180190#define AGGRE2_SNOC_NORTH_AXI 181191#define SSC_XO 182192#define SSC_CNOC_AHBS_CLK 183193#define GCC_MMSS_GPLL0_DIV_CLK 184194#define GCC_GPU_GPLL0_DIV_CLK 185195#define GCC_GPU_GPLL0_CLK 186196#define HLOS1_VOTE_LPASS_CORE_SMMU_CLK 187197#define HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 188198#define GCC_MSS_Q6_BIMC_AXI_CLK 189199 200#define PCIE_0_GDSC 0201#define UFS_GDSC 1202#define USB_30_GDSC 2203#define LPASS_ADSP_GDSC 3204#define LPASS_CORE_GDSC 4205 206#define GCC_BLSP1_QUP1_BCR 0207#define GCC_BLSP1_QUP2_BCR 1208#define GCC_BLSP1_QUP3_BCR 2209#define GCC_BLSP1_QUP4_BCR 3210#define GCC_BLSP1_QUP5_BCR 4211#define GCC_BLSP1_QUP6_BCR 5212#define GCC_BLSP2_QUP1_BCR 6213#define GCC_BLSP2_QUP2_BCR 7214#define GCC_BLSP2_QUP3_BCR 8215#define GCC_BLSP2_QUP4_BCR 9216#define GCC_BLSP2_QUP5_BCR 10217#define GCC_BLSP2_QUP6_BCR 11218#define GCC_PCIE_0_BCR 12219#define GCC_PDM_BCR 13220#define GCC_SDCC2_BCR 14221#define GCC_SDCC4_BCR 15222#define GCC_TSIF_BCR 16223#define GCC_UFS_BCR 17224#define GCC_USB_30_BCR 18225#define GCC_SYSTEM_NOC_BCR 19226#define GCC_CONFIG_NOC_BCR 20227#define GCC_AHB2PHY_EAST_BCR 21228#define GCC_IMEM_BCR 22229#define GCC_PIMEM_BCR 23230#define GCC_MMSS_BCR 24231#define GCC_QDSS_BCR 25232#define GCC_WCSS_BCR 26233#define GCC_BLSP1_BCR 27234#define GCC_BLSP1_UART1_BCR 28235#define GCC_BLSP1_UART2_BCR 29236#define GCC_BLSP1_UART3_BCR 30237#define GCC_CM_PHY_REFGEN1_BCR 31238#define GCC_CM_PHY_REFGEN2_BCR 32239#define GCC_BLSP2_BCR 33240#define GCC_BLSP2_UART1_BCR 34241#define GCC_BLSP2_UART2_BCR 35242#define GCC_BLSP2_UART3_BCR 36243#define GCC_SRAM_SENSOR_BCR 37244#define GCC_PRNG_BCR 38245#define GCC_TSIF_0_RESET 39246#define GCC_TSIF_1_RESET 40247#define GCC_TCSR_BCR 41248#define GCC_BOOT_ROM_BCR 42249#define GCC_MSG_RAM_BCR 43250#define GCC_TLMM_BCR 44251#define GCC_MPM_BCR 45252#define GCC_SEC_CTRL_BCR 46253#define GCC_SPMI_BCR 47254#define GCC_SPDM_BCR 48255#define GCC_CE1_BCR 49256#define GCC_BIMC_BCR 50257#define GCC_SNOC_BUS_TIMEOUT0_BCR 51258#define GCC_SNOC_BUS_TIMEOUT1_BCR 52259#define GCC_SNOC_BUS_TIMEOUT3_BCR 53260#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 54261#define GCC_PNOC_BUS_TIMEOUT0_BCR 55262#define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR 56263#define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR 57264#define GCC_CNOC_BUS_TIMEOUT0_BCR 58265#define GCC_CNOC_BUS_TIMEOUT1_BCR 59266#define GCC_CNOC_BUS_TIMEOUT2_BCR 60267#define GCC_CNOC_BUS_TIMEOUT3_BCR 61268#define GCC_CNOC_BUS_TIMEOUT4_BCR 62269#define GCC_CNOC_BUS_TIMEOUT5_BCR 63270#define GCC_CNOC_BUS_TIMEOUT6_BCR 64271#define GCC_CNOC_BUS_TIMEOUT7_BCR 65272#define GCC_APB2JTAG_BCR 66273#define GCC_RBCPR_CX_BCR 67274#define GCC_RBCPR_MX_BCR 68275#define GCC_USB3_PHY_BCR 69276#define GCC_USB3PHY_PHY_BCR 70277#define GCC_USB3_DP_PHY_BCR 71278#define GCC_SSC_BCR 72279#define GCC_SSC_RESET 73280#define GCC_USB_PHY_CFG_AHB2PHY_BCR 74281#define GCC_PCIE_0_LINK_DOWN_BCR 75282#define GCC_PCIE_0_PHY_BCR 76283#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 77284#define GCC_PCIE_PHY_BCR 78285#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 79286#define GCC_PCIE_PHY_CFG_AHB_BCR 80287#define GCC_PCIE_PHY_COM_BCR 81288#define GCC_GPU_BCR 82289#define GCC_SPSS_BCR 83290#define GCC_OBT_ODT_BCR 84291#define GCC_VS_BCR 85292#define GCC_MSS_VS_RESET 86293#define GCC_GPU_VS_RESET 87294#define GCC_APC0_VS_RESET 88295#define GCC_APC1_VS_RESET 89296#define GCC_CNOC_BUS_TIMEOUT8_BCR 90297#define GCC_CNOC_BUS_TIMEOUT9_BCR 91298#define GCC_CNOC_BUS_TIMEOUT10_BCR 92299#define GCC_CNOC_BUS_TIMEOUT11_BCR 93300#define GCC_CNOC_BUS_TIMEOUT12_BCR 94301#define GCC_CNOC_BUS_TIMEOUT13_BCR 95302#define GCC_CNOC_BUS_TIMEOUT14_BCR 96303#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 97304#define GCC_AGGRE1_NOC_BCR 98305#define GCC_AGGRE2_NOC_BCR 99306#define GCC_DCC_BCR 100307#define GCC_QREFS_VBG_CAL_BCR 101308#define GCC_IPA_BCR 102309#define GCC_GLM_BCR 103310#define GCC_SKL_BCR 104311#define GCC_MSMPU_BCR 105312#define GCC_QUSB2PHY_PRIM_BCR 106313#define GCC_QUSB2PHY_SEC_BCR 107314#define GCC_MSS_RESTART 108315 316#endif317