189 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.4 */5 6#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCM2290_H7#define _DT_BINDINGS_CLK_QCOM_GCC_QCM2290_H8 9/* GCC clocks */10#define GPLL0 011#define GPLL0_OUT_AUX2 112#define GPLL1 213#define GPLL10 314#define GPLL11 415#define GPLL3 516#define GPLL3_OUT_MAIN 617#define GPLL4 718#define GPLL5 819#define GPLL6 920#define GPLL6_OUT_MAIN 1021#define GPLL7 1122#define GPLL8 1223#define GPLL8_OUT_MAIN 1324#define GPLL9 1425#define GPLL9_OUT_MAIN 1526#define GCC_AHB2PHY_CSI_CLK 1627#define GCC_AHB2PHY_USB_CLK 1728#define GCC_APC_VS_CLK 1829#define GCC_BIMC_GPU_AXI_CLK 1930#define GCC_BOOT_ROM_AHB_CLK 2031#define GCC_CAM_THROTTLE_NRT_CLK 2132#define GCC_CAM_THROTTLE_RT_CLK 2233#define GCC_CAMERA_AHB_CLK 2334#define GCC_CAMERA_XO_CLK 2435#define GCC_CAMSS_AXI_CLK 2536#define GCC_CAMSS_AXI_CLK_SRC 2637#define GCC_CAMSS_CAMNOC_ATB_CLK 2738#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 2839#define GCC_CAMSS_CCI_0_CLK 2940#define GCC_CAMSS_CCI_CLK_SRC 3041#define GCC_CAMSS_CPHY_0_CLK 3142#define GCC_CAMSS_CPHY_1_CLK 3243#define GCC_CAMSS_CSI0PHYTIMER_CLK 3344#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 3445#define GCC_CAMSS_CSI1PHYTIMER_CLK 3546#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 3647#define GCC_CAMSS_MCLK0_CLK 3748#define GCC_CAMSS_MCLK0_CLK_SRC 3849#define GCC_CAMSS_MCLK1_CLK 3950#define GCC_CAMSS_MCLK1_CLK_SRC 4051#define GCC_CAMSS_MCLK2_CLK 4152#define GCC_CAMSS_MCLK2_CLK_SRC 4253#define GCC_CAMSS_MCLK3_CLK 4354#define GCC_CAMSS_MCLK3_CLK_SRC 4455#define GCC_CAMSS_NRT_AXI_CLK 4556#define GCC_CAMSS_OPE_AHB_CLK 4657#define GCC_CAMSS_OPE_AHB_CLK_SRC 4758#define GCC_CAMSS_OPE_CLK 4859#define GCC_CAMSS_OPE_CLK_SRC 4960#define GCC_CAMSS_RT_AXI_CLK 5061#define GCC_CAMSS_TFE_0_CLK 5162#define GCC_CAMSS_TFE_0_CLK_SRC 5263#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 5364#define GCC_CAMSS_TFE_0_CSID_CLK 5465#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 5566#define GCC_CAMSS_TFE_1_CLK 5667#define GCC_CAMSS_TFE_1_CLK_SRC 5768#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 5869#define GCC_CAMSS_TFE_1_CSID_CLK 5970#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 6071#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 6172#define GCC_CAMSS_TOP_AHB_CLK 6273#define GCC_CAMSS_TOP_AHB_CLK_SRC 6374#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 6475#define GCC_CPUSS_AHB_CLK 6576#define GCC_CPUSS_AHB_CLK_SRC 6677#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 6778#define GCC_CPUSS_GNOC_CLK 6879#define GCC_CPUSS_THROTTLE_CORE_CLK 6980#define GCC_CPUSS_THROTTLE_XO_CLK 7081#define GCC_DISP_AHB_CLK 7182#define GCC_DISP_GPLL0_CLK_SRC 7283#define GCC_DISP_GPLL0_DIV_CLK_SRC 7384#define GCC_DISP_HF_AXI_CLK 7485#define GCC_DISP_THROTTLE_CORE_CLK 7586#define GCC_DISP_XO_CLK 7687#define GCC_GP1_CLK 7788#define GCC_GP1_CLK_SRC 7889#define GCC_GP2_CLK 7990#define GCC_GP2_CLK_SRC 8091#define GCC_GP3_CLK 8192#define GCC_GP3_CLK_SRC 8293#define GCC_GPU_CFG_AHB_CLK 8394#define GCC_GPU_GPLL0_CLK_SRC 8495#define GCC_GPU_GPLL0_DIV_CLK_SRC 8596#define GCC_GPU_IREF_CLK 8697#define GCC_GPU_MEMNOC_GFX_CLK 8798#define GCC_GPU_SNOC_DVM_GFX_CLK 8899#define GCC_GPU_THROTTLE_CORE_CLK 89100#define GCC_GPU_THROTTLE_XO_CLK 90101#define GCC_PDM2_CLK 91102#define GCC_PDM2_CLK_SRC 92103#define GCC_PDM_AHB_CLK 93104#define GCC_PDM_XO4_CLK 94105#define GCC_PWM0_XO512_CLK 95106#define GCC_QMIP_CAMERA_NRT_AHB_CLK 96107#define GCC_QMIP_CAMERA_RT_AHB_CLK 97108#define GCC_QMIP_CPUSS_CFG_AHB_CLK 98109#define GCC_QMIP_DISP_AHB_CLK 99110#define GCC_QMIP_GPU_CFG_AHB_CLK 100111#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 101112#define GCC_QUPV3_WRAP0_CORE_2X_CLK 102113#define GCC_QUPV3_WRAP0_CORE_CLK 103114#define GCC_QUPV3_WRAP0_S0_CLK 104115#define GCC_QUPV3_WRAP0_S0_CLK_SRC 105116#define GCC_QUPV3_WRAP0_S1_CLK 106117#define GCC_QUPV3_WRAP0_S1_CLK_SRC 107118#define GCC_QUPV3_WRAP0_S2_CLK 108119#define GCC_QUPV3_WRAP0_S2_CLK_SRC 109120#define GCC_QUPV3_WRAP0_S3_CLK 110121#define GCC_QUPV3_WRAP0_S3_CLK_SRC 111122#define GCC_QUPV3_WRAP0_S4_CLK 112123#define GCC_QUPV3_WRAP0_S4_CLK_SRC 113124#define GCC_QUPV3_WRAP0_S5_CLK 114125#define GCC_QUPV3_WRAP0_S5_CLK_SRC 115126#define GCC_QUPV3_WRAP_0_M_AHB_CLK 116127#define GCC_QUPV3_WRAP_0_S_AHB_CLK 117128#define GCC_SDCC1_AHB_CLK 118129#define GCC_SDCC1_APPS_CLK 119130#define GCC_SDCC1_APPS_CLK_SRC 120131#define GCC_SDCC1_ICE_CORE_CLK 121132#define GCC_SDCC1_ICE_CORE_CLK_SRC 122133#define GCC_SDCC2_AHB_CLK 123134#define GCC_SDCC2_APPS_CLK 124135#define GCC_SDCC2_APPS_CLK_SRC 125136#define GCC_SYS_NOC_CPUSS_AHB_CLK 126137#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 127138#define GCC_USB30_PRIM_MASTER_CLK 128139#define GCC_USB30_PRIM_MASTER_CLK_SRC 129140#define GCC_USB30_PRIM_MOCK_UTMI_CLK 130141#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 131142#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV 132143#define GCC_USB30_PRIM_SLEEP_CLK 133144#define GCC_USB3_PRIM_CLKREF_CLK 134145#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 135146#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 136147#define GCC_USB3_PRIM_PHY_PIPE_CLK 137148#define GCC_VCODEC0_AXI_CLK 138149#define GCC_VENUS_AHB_CLK 139150#define GCC_VENUS_CTL_AXI_CLK 140151#define GCC_VIDEO_AHB_CLK 141152#define GCC_VIDEO_AXI0_CLK 142153#define GCC_VIDEO_THROTTLE_CORE_CLK 143154#define GCC_VIDEO_VCODEC0_SYS_CLK 144155#define GCC_VIDEO_VENUS_CLK_SRC 145156#define GCC_VIDEO_VENUS_CTL_CLK 146157#define GCC_VIDEO_XO_CLK 147158 159/* GCC resets */160#define GCC_CAMSS_OPE_BCR 0161#define GCC_CAMSS_TFE_BCR 1162#define GCC_CAMSS_TOP_BCR 2163#define GCC_GPU_BCR 3164#define GCC_MMSS_BCR 4165#define GCC_PDM_BCR 5166#define GCC_QUPV3_WRAPPER_0_BCR 6167#define GCC_SDCC1_BCR 7168#define GCC_SDCC2_BCR 8169#define GCC_USB30_PRIM_BCR 9170#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10171#define GCC_VCODEC0_BCR 11172#define GCC_VENUS_BCR 12173#define GCC_VIDEO_INTERFACE_BCR 13174#define GCC_QUSB2PHY_PRIM_BCR 14175#define GCC_USB3_PHY_PRIM_SP0_BCR 15176#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 16177 178/* Indexes for GDSCs */179#define GCC_CAMSS_TOP_GDSC 0180#define GCC_USB30_PRIM_GDSC 1181#define GCC_VCODEC0_GDSC 2182#define GCC_VENUS_GDSC 3183#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 4184#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 5185#define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC 6186#define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC 7187 188#endif189