185 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.4 */5 6#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H7#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H8 9#define GCC_APSS_AHB_CLK_SRC 010#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 111#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 212#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 313#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 414#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 515#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 616#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 717#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 818#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 919#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 1020#define GCC_BLSP1_UART0_APPS_CLK_SRC 1121#define GCC_BLSP1_UART1_APPS_CLK_SRC 1222#define GCC_BLSP1_UART2_APPS_CLK_SRC 1323#define GCC_BLSP1_UART3_APPS_CLK_SRC 1424#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 1525#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 1626#define GCC_BLSP2_UART0_APPS_CLK_SRC 1727#define GCC_BYTE0_CLK_SRC 1828#define GCC_EMAC_CLK_SRC 1929#define GCC_EMAC_PTP_CLK_SRC 2030#define GCC_ESC0_CLK_SRC 2131#define GCC_APSS_AHB_CLK 2232#define GCC_APSS_AXI_CLK 2333#define GCC_BIMC_APSS_AXI_CLK 2434#define GCC_BIMC_GFX_CLK 2535#define GCC_BIMC_MDSS_CLK 2636#define GCC_BLSP1_AHB_CLK 2737#define GCC_BLSP1_QUP0_I2C_APPS_CLK 2838#define GCC_BLSP1_QUP0_SPI_APPS_CLK 2939#define GCC_BLSP1_QUP1_I2C_APPS_CLK 3040#define GCC_BLSP1_QUP1_SPI_APPS_CLK 3141#define GCC_BLSP1_QUP2_I2C_APPS_CLK 3242#define GCC_BLSP1_QUP2_SPI_APPS_CLK 3343#define GCC_BLSP1_QUP3_I2C_APPS_CLK 3444#define GCC_BLSP1_QUP3_SPI_APPS_CLK 3545#define GCC_BLSP1_QUP4_I2C_APPS_CLK 3646#define GCC_BLSP1_QUP4_SPI_APPS_CLK 3747#define GCC_BLSP1_UART0_APPS_CLK 3848#define GCC_BLSP1_UART1_APPS_CLK 3949#define GCC_BLSP1_UART2_APPS_CLK 4050#define GCC_BLSP1_UART3_APPS_CLK 4151#define GCC_BLSP2_AHB_CLK 4252#define GCC_BLSP2_QUP0_I2C_APPS_CLK 4353#define GCC_BLSP2_QUP0_SPI_APPS_CLK 4454#define GCC_BLSP2_UART0_APPS_CLK 4555#define GCC_BOOT_ROM_AHB_CLK 4656#define GCC_DCC_CLK 4757#define GCC_GENI_IR_H_CLK 4858#define GCC_ETH_AXI_CLK 4959#define GCC_ETH_PTP_CLK 5060#define GCC_ETH_RGMII_CLK 5161#define GCC_ETH_SLAVE_AHB_CLK 5262#define GCC_GENI_IR_S_CLK 5363#define GCC_GP1_CLK 5464#define GCC_GP2_CLK 5565#define GCC_GP3_CLK 5666#define GCC_MDSS_AHB_CLK 5767#define GCC_MDSS_AXI_CLK 5868#define GCC_MDSS_BYTE0_CLK 5969#define GCC_MDSS_ESC0_CLK 6070#define GCC_MDSS_HDMI_APP_CLK 6171#define GCC_MDSS_HDMI_PCLK_CLK 6272#define GCC_MDSS_MDP_CLK 6373#define GCC_MDSS_PCLK0_CLK 6474#define GCC_MDSS_VSYNC_CLK 6575#define GCC_OXILI_AHB_CLK 6676#define GCC_OXILI_GFX3D_CLK 6777#define GCC_PCIE_0_AUX_CLK 6878#define GCC_PCIE_0_CFG_AHB_CLK 6979#define GCC_PCIE_0_MSTR_AXI_CLK 7080#define GCC_PCIE_0_PIPE_CLK 7181#define GCC_PCIE_0_SLV_AXI_CLK 7282#define GCC_PCNOC_USB2_CLK 7383#define GCC_PCNOC_USB3_CLK 7484#define GCC_PDM2_CLK 7585#define GCC_PDM_AHB_CLK 7686#define GCC_VSYNC_CLK_SRC 7787#define GCC_PRNG_AHB_CLK 7888#define GCC_PWM0_XO512_CLK 7989#define GCC_PWM1_XO512_CLK 8090#define GCC_PWM2_XO512_CLK 8191#define GCC_SDCC1_AHB_CLK 8292#define GCC_SDCC1_APPS_CLK 8393#define GCC_SDCC1_ICE_CORE_CLK 8494#define GCC_SDCC2_AHB_CLK 8595#define GCC_SDCC2_APPS_CLK 8696#define GCC_SYS_NOC_USB3_CLK 8797#define GCC_USB20_MOCK_UTMI_CLK 8898#define GCC_USB2A_PHY_SLEEP_CLK 8999#define GCC_USB30_MASTER_CLK 90100#define GCC_USB30_MOCK_UTMI_CLK 91101#define GCC_USB30_SLEEP_CLK 92102#define GCC_USB3_PHY_AUX_CLK 93103#define GCC_USB3_PHY_PIPE_CLK 94104#define GCC_USB_HS_PHY_CFG_AHB_CLK 95105#define GCC_USB_HS_SYSTEM_CLK 96106#define GCC_GFX3D_CLK_SRC 97107#define GCC_GP1_CLK_SRC 98108#define GCC_GP2_CLK_SRC 99109#define GCC_GP3_CLK_SRC 100110#define GCC_GPLL0_OUT_MAIN 101111#define GCC_GPLL1_OUT_MAIN 102112#define GCC_GPLL3_OUT_MAIN 103113#define GCC_GPLL4_OUT_MAIN 104114#define GCC_HDMI_APP_CLK_SRC 105115#define GCC_HDMI_PCLK_CLK_SRC 106116#define GCC_MDP_CLK_SRC 107117#define GCC_PCIE_0_AUX_CLK_SRC 108118#define GCC_PCIE_0_PIPE_CLK_SRC 109119#define GCC_PCLK0_CLK_SRC 110120#define GCC_PDM2_CLK_SRC 111121#define GCC_SDCC1_APPS_CLK_SRC 112122#define GCC_SDCC1_ICE_CORE_CLK_SRC 113123#define GCC_SDCC2_APPS_CLK_SRC 114124#define GCC_USB20_MOCK_UTMI_CLK_SRC 115125#define GCC_USB30_MASTER_CLK_SRC 116126#define GCC_USB30_MOCK_UTMI_CLK_SRC 117127#define GCC_USB3_PHY_AUX_CLK_SRC 118128#define GCC_USB_HS_SYSTEM_CLK_SRC 119129#define GCC_GPLL0_AO_CLK_SRC 120130#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122131#define GCC_GPLL0_AO_OUT_MAIN 123132#define GCC_GPLL0_SLEEP_CLK_SRC 124133#define GCC_GPLL6 125134#define GCC_GPLL6_OUT_AUX 126135#define GCC_MDSS_MDP_VOTE_CLK 127136#define GCC_MDSS_ROTATOR_VOTE_CLK 128137#define GCC_BIMC_GPU_CLK 129138#define GCC_GTCU_AHB_CLK 130139#define GCC_GFX_TCU_CLK 131140#define GCC_GFX_TBU_CLK 132141#define GCC_SMMU_CFG_CLK 133142#define GCC_APSS_TCU_CLK 134143#define GCC_CRYPTO_AHB_CLK 135144#define GCC_CRYPTO_AXI_CLK 136145#define GCC_CRYPTO_CLK 137146#define GCC_MDP_TBU_CLK 138147#define GCC_QDSS_DAP_CLK 139148#define GCC_DCC_XO_CLK 140149#define GCC_WCSS_Q6_AHB_CLK 141150#define GCC_WCSS_Q6_AXIM_CLK 142151#define GCC_CDSP_CFG_AHB_CLK 143152#define GCC_BIMC_CDSP_CLK 144153#define GCC_CDSP_TBU_CLK 145154#define GCC_CDSP_BIMC_CLK_SRC 146155 156#define GCC_GENI_IR_BCR 0157#define GCC_USB_HS_BCR 1158#define GCC_USB2_HS_PHY_ONLY_BCR 2159#define GCC_QUSB2_PHY_BCR 3160#define GCC_USB_HS_PHY_CFG_AHB_BCR 4161#define GCC_USB2A_PHY_BCR 5162#define GCC_USB3_PHY_BCR 6163#define GCC_USB_30_BCR 7164#define GCC_USB3PHY_PHY_BCR 8165#define GCC_PCIE_0_BCR 9166#define GCC_PCIE_0_PHY_BCR 10167#define GCC_PCIE_0_LINK_DOWN_BCR 11168#define GCC_PCIEPHY_0_PHY_BCR 12169#define GCC_EMAC_BCR 13170#define GCC_CDSP_RESTART 14171#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15172#define GCC_PCIE_0_AHB_ARES 16173#define GCC_PCIE_0_AXI_SLAVE_ARES 17174#define GCC_PCIE_0_AXI_MASTER_ARES 18175#define GCC_PCIE_0_CORE_STICKY_ARES 19176#define GCC_PCIE_0_SLEEP_ARES 20177#define GCC_PCIE_0_PIPE_ARES 21178#define GCC_WDSP_RESTART 22179 180/* Indexes for GDSCs */181#define MDSS_GDSC 0182#define OXILI_GDSC 1183 184#endif185