163 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.4 */5 6#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H7#define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H8 9/* GCC clocks */10#define GCC_GPLL0_MAIN_DIV_CDIV 011#define GPLL0 112#define GPLL0_OUT_EVEN 213#define GPLL1 314#define GPLL4 415#define GPLL6 516#define GPLL7 617#define GCC_AGGRE_UFS_PHY_AXI_CLK 718#define GCC_AGGRE_USB3_PRIM_AXI_CLK 819#define GCC_BOOT_ROM_AHB_CLK 920#define GCC_CAMERA_AHB_CLK 1021#define GCC_CAMERA_HF_AXI_CLK 1122#define GCC_CAMERA_THROTTLE_HF_AXI_CLK 1223#define GCC_CAMERA_XO_CLK 1324#define GCC_CE1_AHB_CLK 1425#define GCC_CE1_AXI_CLK 1526#define GCC_CE1_CLK 1627#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 1728#define GCC_CPUSS_AHB_CLK 1829#define GCC_CPUSS_AHB_CLK_SRC 1930#define GCC_CPUSS_GNOC_CLK 2031#define GCC_CPUSS_RBCPR_CLK 2132#define GCC_DDRSS_GPU_AXI_CLK 2233#define GCC_DISP_AHB_CLK 2334#define GCC_DISP_GPLL0_CLK_SRC 2435#define GCC_DISP_GPLL0_DIV_CLK_SRC 2536#define GCC_DISP_HF_AXI_CLK 2637#define GCC_DISP_THROTTLE_HF_AXI_CLK 2738#define GCC_DISP_XO_CLK 2839#define GCC_GP1_CLK 2940#define GCC_GP1_CLK_SRC 3041#define GCC_GP2_CLK 3142#define GCC_GP2_CLK_SRC 3243#define GCC_GP3_CLK 3344#define GCC_GP3_CLK_SRC 3445#define GCC_GPU_CFG_AHB_CLK 3546#define GCC_GPU_GPLL0_CLK_SRC 3647#define GCC_GPU_GPLL0_DIV_CLK_SRC 3748#define GCC_GPU_MEMNOC_GFX_CLK 3849#define GCC_GPU_SNOC_DVM_GFX_CLK 3950#define GCC_NPU_AXI_CLK 4051#define GCC_NPU_BWMON_AXI_CLK 4152#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 4253#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 4354#define GCC_NPU_CFG_AHB_CLK 4455#define GCC_NPU_DMA_CLK 4556#define GCC_NPU_GPLL0_CLK_SRC 4657#define GCC_NPU_GPLL0_DIV_CLK_SRC 4758#define GCC_PDM2_CLK 4859#define GCC_PDM2_CLK_SRC 4960#define GCC_PDM_AHB_CLK 5061#define GCC_PDM_XO4_CLK 5162#define GCC_PRNG_AHB_CLK 5263#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 5364#define GCC_QSPI_CORE_CLK 5465#define GCC_QSPI_CORE_CLK_SRC 5566#define GCC_QUPV3_WRAP0_CORE_2X_CLK 5667#define GCC_QUPV3_WRAP0_CORE_CLK 5768#define GCC_QUPV3_WRAP0_S0_CLK 5869#define GCC_QUPV3_WRAP0_S0_CLK_SRC 5970#define GCC_QUPV3_WRAP0_S1_CLK 6071#define GCC_QUPV3_WRAP0_S1_CLK_SRC 6172#define GCC_QUPV3_WRAP0_S2_CLK 6273#define GCC_QUPV3_WRAP0_S2_CLK_SRC 6374#define GCC_QUPV3_WRAP0_S3_CLK 6475#define GCC_QUPV3_WRAP0_S3_CLK_SRC 6576#define GCC_QUPV3_WRAP0_S4_CLK 6677#define GCC_QUPV3_WRAP0_S4_CLK_SRC 6778#define GCC_QUPV3_WRAP0_S5_CLK 6879#define GCC_QUPV3_WRAP0_S5_CLK_SRC 6980#define GCC_QUPV3_WRAP1_CORE_2X_CLK 7081#define GCC_QUPV3_WRAP1_CORE_CLK 7182#define GCC_QUPV3_WRAP1_S0_CLK 7283#define GCC_QUPV3_WRAP1_S0_CLK_SRC 7384#define GCC_QUPV3_WRAP1_S1_CLK 7485#define GCC_QUPV3_WRAP1_S1_CLK_SRC 7586#define GCC_QUPV3_WRAP1_S2_CLK 7687#define GCC_QUPV3_WRAP1_S2_CLK_SRC 7788#define GCC_QUPV3_WRAP1_S3_CLK 7889#define GCC_QUPV3_WRAP1_S3_CLK_SRC 7990#define GCC_QUPV3_WRAP1_S4_CLK 8091#define GCC_QUPV3_WRAP1_S4_CLK_SRC 8192#define GCC_QUPV3_WRAP1_S5_CLK 8293#define GCC_QUPV3_WRAP1_S5_CLK_SRC 8394#define GCC_QUPV3_WRAP_0_M_AHB_CLK 8495#define GCC_QUPV3_WRAP_0_S_AHB_CLK 8596#define GCC_QUPV3_WRAP_1_M_AHB_CLK 8697#define GCC_QUPV3_WRAP_1_S_AHB_CLK 8798#define GCC_SDCC1_AHB_CLK 8899#define GCC_SDCC1_APPS_CLK 89100#define GCC_SDCC1_APPS_CLK_SRC 90101#define GCC_SDCC1_ICE_CORE_CLK 91102#define GCC_SDCC1_ICE_CORE_CLK_SRC 92103#define GCC_SDCC2_AHB_CLK 93104#define GCC_SDCC2_APPS_CLK 94105#define GCC_SDCC2_APPS_CLK_SRC 95106#define GCC_SYS_NOC_CPUSS_AHB_CLK 96107#define GCC_UFS_MEM_CLKREF_CLK 97108#define GCC_UFS_PHY_AHB_CLK 98109#define GCC_UFS_PHY_AXI_CLK 99110#define GCC_UFS_PHY_AXI_CLK_SRC 100111#define GCC_UFS_PHY_ICE_CORE_CLK 101112#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102113#define GCC_UFS_PHY_PHY_AUX_CLK 103114#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104115#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105116#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106117#define GCC_UFS_PHY_UNIPRO_CORE_CLK 107118#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108119#define GCC_USB30_PRIM_MASTER_CLK 109120#define GCC_USB30_PRIM_MASTER_CLK_SRC 110121#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111122#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112123#define GCC_USB30_PRIM_SLEEP_CLK 113124#define GCC_USB3_PRIM_CLKREF_CLK 114125#define GCC_USB3_PRIM_PHY_AUX_CLK 115126#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116127#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117128#define GCC_USB3_PRIM_PHY_PIPE_CLK 118129#define GCC_USB_PHY_CFG_AHB2PHY_CLK 119130#define GCC_VIDEO_AHB_CLK 120131#define GCC_VIDEO_AXI_CLK 121132#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122133#define GCC_VIDEO_THROTTLE_AXI_CLK 123134#define GCC_VIDEO_XO_CLK 124135#define GCC_MSS_CFG_AHB_CLK 125136#define GCC_MSS_MFAB_AXIS_CLK 126137#define GCC_MSS_NAV_AXI_CLK 127138#define GCC_MSS_Q6_MEMNOC_AXI_CLK 128139#define GCC_MSS_SNOC_AXI_CLK 129140#define GCC_SEC_CTRL_CLK_SRC 130141#define GCC_LPASS_CFG_NOC_SWAY_CLK 131142 143/* GCC resets */144#define GCC_QUSB2PHY_PRIM_BCR 0145#define GCC_QUSB2PHY_SEC_BCR 1146#define GCC_UFS_PHY_BCR 2147#define GCC_USB30_PRIM_BCR 3148#define GCC_USB3_DP_PHY_PRIM_BCR 4149#define GCC_USB3_DP_PHY_SEC_BCR 5150#define GCC_USB3_PHY_PRIM_BCR 6151#define GCC_USB3_PHY_SEC_BCR 7152#define GCC_USB3PHY_PHY_PRIM_BCR 8153#define GCC_USB3PHY_PHY_SEC_BCR 9154#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10155 156/* GCC GDSCRs */157#define UFS_PHY_GDSC 0158#define USB30_PRIM_GDSC 1159#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2160#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3161 162#endif163