227 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.4 */5 6#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7280_H7#define _DT_BINDINGS_CLK_QCOM_GCC_SC7280_H8 9/* GCC clocks */10#define GCC_GPLL0 011#define GCC_GPLL0_OUT_EVEN 112#define GCC_GPLL0_OUT_ODD 213#define GCC_GPLL1 314#define GCC_GPLL10 415#define GCC_GPLL4 516#define GCC_GPLL9 617#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 718#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 819#define GCC_AGGRE_UFS_PHY_AXI_CLK 920#define GCC_AGGRE_USB3_PRIM_AXI_CLK 1021#define GCC_CAMERA_AHB_CLK 1122#define GCC_CAMERA_HF_AXI_CLK 1223#define GCC_CAMERA_SF_AXI_CLK 1324#define GCC_CAMERA_XO_CLK 1425#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 1526#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 1627#define GCC_CPUSS_AHB_CLK 1728#define GCC_CPUSS_AHB_CLK_SRC 1829#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 1930#define GCC_DDRSS_GPU_AXI_CLK 2031#define GCC_DDRSS_PCIE_SF_CLK 2132#define GCC_DISP_AHB_CLK 2233#define GCC_DISP_GPLL0_CLK_SRC 2334#define GCC_DISP_HF_AXI_CLK 2435#define GCC_DISP_SF_AXI_CLK 2536#define GCC_DISP_XO_CLK 2637#define GCC_GP1_CLK 2738#define GCC_GP1_CLK_SRC 2839#define GCC_GP2_CLK 2940#define GCC_GP2_CLK_SRC 3041#define GCC_GP3_CLK 3142#define GCC_GP3_CLK_SRC 3243#define GCC_GPU_CFG_AHB_CLK 3344#define GCC_GPU_GPLL0_CLK_SRC 3445#define GCC_GPU_GPLL0_DIV_CLK_SRC 3546#define GCC_GPU_IREF_EN 3647#define GCC_GPU_MEMNOC_GFX_CLK 3748#define GCC_GPU_SNOC_DVM_GFX_CLK 3849#define GCC_PCIE0_PHY_RCHNG_CLK 3950#define GCC_PCIE1_PHY_RCHNG_CLK 4051#define GCC_PCIE_0_AUX_CLK 4152#define GCC_PCIE_0_AUX_CLK_SRC 4253#define GCC_PCIE_0_CFG_AHB_CLK 4354#define GCC_PCIE_0_MSTR_AXI_CLK 4455#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 4556#define GCC_PCIE_0_PIPE_CLK 4657#define GCC_PCIE_0_PIPE_CLK_SRC 4758#define GCC_PCIE_0_SLV_AXI_CLK 4859#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 4960#define GCC_PCIE_1_AUX_CLK 5061#define GCC_PCIE_1_AUX_CLK_SRC 5162#define GCC_PCIE_1_CFG_AHB_CLK 5263#define GCC_PCIE_1_MSTR_AXI_CLK 5364#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 5465#define GCC_PCIE_1_PIPE_CLK 5566#define GCC_PCIE_1_PIPE_CLK_SRC 5667#define GCC_PCIE_1_SLV_AXI_CLK 5768#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 5869#define GCC_PCIE_THROTTLE_CORE_CLK 5970#define GCC_PDM2_CLK 6071#define GCC_PDM2_CLK_SRC 6172#define GCC_PDM_AHB_CLK 6273#define GCC_PDM_XO4_CLK 6374#define GCC_QMIP_CAMERA_NRT_AHB_CLK 6475#define GCC_QMIP_CAMERA_RT_AHB_CLK 6576#define GCC_QMIP_DISP_AHB_CLK 6677#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 6778#define GCC_QUPV3_WRAP0_CORE_2X_CLK 6879#define GCC_QUPV3_WRAP0_CORE_CLK 6980#define GCC_QUPV3_WRAP0_S0_CLK 7081#define GCC_QUPV3_WRAP0_S0_CLK_SRC 7182#define GCC_QUPV3_WRAP0_S1_CLK 7283#define GCC_QUPV3_WRAP0_S1_CLK_SRC 7384#define GCC_QUPV3_WRAP0_S2_CLK 7485#define GCC_QUPV3_WRAP0_S2_CLK_SRC 7586#define GCC_QUPV3_WRAP0_S3_CLK 7687#define GCC_QUPV3_WRAP0_S3_CLK_SRC 7788#define GCC_QUPV3_WRAP0_S4_CLK 7889#define GCC_QUPV3_WRAP0_S4_CLK_SRC 7990#define GCC_QUPV3_WRAP0_S5_CLK 8091#define GCC_QUPV3_WRAP0_S5_CLK_SRC 8192#define GCC_QUPV3_WRAP0_S6_CLK 8293#define GCC_QUPV3_WRAP0_S6_CLK_SRC 8394#define GCC_QUPV3_WRAP0_S7_CLK 8495#define GCC_QUPV3_WRAP0_S7_CLK_SRC 8596#define GCC_QUPV3_WRAP1_CORE_2X_CLK 8697#define GCC_QUPV3_WRAP1_CORE_CLK 8798#define GCC_QUPV3_WRAP1_S0_CLK 8899#define GCC_QUPV3_WRAP1_S0_CLK_SRC 89100#define GCC_QUPV3_WRAP1_S1_CLK 90101#define GCC_QUPV3_WRAP1_S1_CLK_SRC 91102#define GCC_QUPV3_WRAP1_S2_CLK 92103#define GCC_QUPV3_WRAP1_S2_CLK_SRC 93104#define GCC_QUPV3_WRAP1_S3_CLK 94105#define GCC_QUPV3_WRAP1_S3_CLK_SRC 95106#define GCC_QUPV3_WRAP1_S4_CLK 96107#define GCC_QUPV3_WRAP1_S4_CLK_SRC 97108#define GCC_QUPV3_WRAP1_S5_CLK 98109#define GCC_QUPV3_WRAP1_S5_CLK_SRC 99110#define GCC_QUPV3_WRAP1_S6_CLK 100111#define GCC_QUPV3_WRAP1_S6_CLK_SRC 101112#define GCC_QUPV3_WRAP1_S7_CLK 102113#define GCC_QUPV3_WRAP1_S7_CLK_SRC 103114#define GCC_QUPV3_WRAP_0_M_AHB_CLK 104115#define GCC_QUPV3_WRAP_0_S_AHB_CLK 105116#define GCC_QUPV3_WRAP_1_M_AHB_CLK 106117#define GCC_QUPV3_WRAP_1_S_AHB_CLK 107118#define GCC_SDCC1_AHB_CLK 108119#define GCC_SDCC1_APPS_CLK 109120#define GCC_SDCC1_APPS_CLK_SRC 110121#define GCC_SDCC1_ICE_CORE_CLK 111122#define GCC_SDCC1_ICE_CORE_CLK_SRC 112123#define GCC_SDCC2_AHB_CLK 113124#define GCC_SDCC2_APPS_CLK 114125#define GCC_SDCC2_APPS_CLK_SRC 115126#define GCC_SDCC4_AHB_CLK 116127#define GCC_SDCC4_APPS_CLK 117128#define GCC_SDCC4_APPS_CLK_SRC 118129#define GCC_SYS_NOC_CPUSS_AHB_CLK 119130#define GCC_THROTTLE_PCIE_AHB_CLK 120131#define GCC_TITAN_NRT_THROTTLE_CORE_CLK 121132#define GCC_TITAN_RT_THROTTLE_CORE_CLK 122133#define GCC_UFS_1_CLKREF_EN 123134#define GCC_UFS_PHY_AHB_CLK 124135#define GCC_UFS_PHY_AXI_CLK 125136#define GCC_UFS_PHY_AXI_CLK_SRC 126137#define GCC_UFS_PHY_ICE_CORE_CLK 127138#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 128139#define GCC_UFS_PHY_PHY_AUX_CLK 129140#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 130141#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 131142#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 132143#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 133144#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 134145#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 135146#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 136147#define GCC_UFS_PHY_UNIPRO_CORE_CLK 137148#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 138149#define GCC_USB30_PRIM_MASTER_CLK 139150#define GCC_USB30_PRIM_MASTER_CLK_SRC 140151#define GCC_USB30_PRIM_MOCK_UTMI_CLK 141152#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 142153#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 143154#define GCC_USB30_PRIM_SLEEP_CLK 144155#define GCC_USB30_SEC_MASTER_CLK 145156#define GCC_USB30_SEC_MASTER_CLK_SRC 146157#define GCC_USB30_SEC_MOCK_UTMI_CLK 147158#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 148159#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 149160#define GCC_USB30_SEC_SLEEP_CLK 150161#define GCC_USB3_PRIM_PHY_AUX_CLK 151162#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 152163#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 153164#define GCC_USB3_PRIM_PHY_PIPE_CLK 154165#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 155166#define GCC_USB3_SEC_PHY_AUX_CLK 156167#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 157168#define GCC_USB3_SEC_PHY_COM_AUX_CLK 158169#define GCC_USB3_SEC_PHY_PIPE_CLK 159170#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 160171#define GCC_VIDEO_AHB_CLK 161172#define GCC_VIDEO_AXI0_CLK 162173#define GCC_VIDEO_MVP_THROTTLE_CORE_CLK 163174#define GCC_VIDEO_XO_CLK 164175#define GCC_GPLL0_MAIN_DIV_CDIV 165176#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 166177#define GCC_QSPI_CORE_CLK 167178#define GCC_QSPI_CORE_CLK_SRC 168179#define GCC_CFG_NOC_LPASS_CLK 169180#define GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC 170181#define GCC_MSS_CFG_AHB_CLK 171182#define GCC_MSS_OFFLINE_AXI_CLK 172183#define GCC_MSS_SNOC_AXI_CLK 173184#define GCC_MSS_Q6_MEMNOC_AXI_CLK 174185#define GCC_MSS_Q6SS_BOOT_CLK_SRC 175186#define GCC_AGGRE_USB3_SEC_AXI_CLK 176187#define GCC_AGGRE_NOC_PCIE_TBU_CLK 177188#define GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK 178189#define GCC_PCIE_CLKREF_EN 179190#define GCC_WPSS_AHB_CLK 180191#define GCC_WPSS_AHB_BDG_MST_CLK 181192#define GCC_WPSS_RSCP_CLK 182193#define GCC_EDP_CLKREF_EN 183194#define GCC_SEC_CTRL_CLK_SRC 184195 196/* GCC power domains */197#define GCC_PCIE_0_GDSC 0198#define GCC_PCIE_1_GDSC 1199#define GCC_UFS_PHY_GDSC 2200#define GCC_USB30_PRIM_GDSC 3201#define GCC_USB30_SEC_GDSC 4202#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 5203#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 6204#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 7205#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 8206#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 9207 208/* GCC resets */209#define GCC_PCIE_0_BCR 0210#define GCC_PCIE_0_PHY_BCR 1211#define GCC_PCIE_1_BCR 2212#define GCC_PCIE_1_PHY_BCR 3213#define GCC_QUSB2PHY_PRIM_BCR 4214#define GCC_QUSB2PHY_SEC_BCR 5215#define GCC_SDCC1_BCR 6216#define GCC_SDCC2_BCR 7217#define GCC_SDCC4_BCR 8218#define GCC_UFS_PHY_BCR 9219#define GCC_USB30_PRIM_BCR 10220#define GCC_USB30_SEC_BCR 11221#define GCC_USB3_DP_PHY_PRIM_BCR 12222#define GCC_USB3_PHY_PRIM_BCR 13223#define GCC_USB3PHY_PHY_PRIM_BCR 14224#define GCC_USB_PHY_CFG_AHB2PHY_BCR 15225 226#endif227