248 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.4 */5 6#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H7#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H8 9/* GCC clock registers */10#define GCC_AGGRE_NOC_PCIE_TBU_CLK 011#define GCC_AGGRE_UFS_CARD_AXI_CLK 112#define GCC_AGGRE_UFS_PHY_AXI_CLK 213#define GCC_AGGRE_USB3_PRIM_AXI_CLK 314#define GCC_AGGRE_USB3_SEC_AXI_CLK 415#define GCC_BOOT_ROM_AHB_CLK 516#define GCC_CAMERA_AHB_CLK 617#define GCC_CAMERA_AXI_CLK 718#define GCC_CAMERA_XO_CLK 819#define GCC_CE1_AHB_CLK 920#define GCC_CE1_AXI_CLK 1021#define GCC_CE1_CLK 1122#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 1223#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 1324#define GCC_CPUSS_AHB_CLK 1425#define GCC_CPUSS_AHB_CLK_SRC 1526#define GCC_CPUSS_RBCPR_CLK 1627#define GCC_CPUSS_RBCPR_CLK_SRC 1728#define GCC_DDRSS_GPU_AXI_CLK 1829#define GCC_DISP_AHB_CLK 1930#define GCC_DISP_AXI_CLK 2031#define GCC_DISP_GPLL0_CLK_SRC 2132#define GCC_DISP_GPLL0_DIV_CLK_SRC 2233#define GCC_DISP_XO_CLK 2334#define GCC_GP1_CLK 2435#define GCC_GP1_CLK_SRC 2536#define GCC_GP2_CLK 2637#define GCC_GP2_CLK_SRC 2738#define GCC_GP3_CLK 2839#define GCC_GP3_CLK_SRC 2940#define GCC_GPU_CFG_AHB_CLK 3041#define GCC_GPU_GPLL0_CLK_SRC 3142#define GCC_GPU_GPLL0_DIV_CLK_SRC 3243#define GCC_GPU_MEMNOC_GFX_CLK 3344#define GCC_GPU_SNOC_DVM_GFX_CLK 3445#define GCC_MSS_AXIS2_CLK 3546#define GCC_MSS_CFG_AHB_CLK 3647#define GCC_MSS_GPLL0_DIV_CLK_SRC 3748#define GCC_MSS_MFAB_AXIS_CLK 3849#define GCC_MSS_Q6_MEMNOC_AXI_CLK 3950#define GCC_MSS_SNOC_AXI_CLK 4051#define GCC_PCIE_0_AUX_CLK 4152#define GCC_PCIE_0_AUX_CLK_SRC 4253#define GCC_PCIE_0_CFG_AHB_CLK 4354#define GCC_PCIE_0_CLKREF_CLK 4455#define GCC_PCIE_0_MSTR_AXI_CLK 4556#define GCC_PCIE_0_PIPE_CLK 4657#define GCC_PCIE_0_SLV_AXI_CLK 4758#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 4859#define GCC_PCIE_1_AUX_CLK 4960#define GCC_PCIE_1_AUX_CLK_SRC 5061#define GCC_PCIE_1_CFG_AHB_CLK 5162#define GCC_PCIE_1_CLKREF_CLK 5263#define GCC_PCIE_1_MSTR_AXI_CLK 5364#define GCC_PCIE_1_PIPE_CLK 5465#define GCC_PCIE_1_SLV_AXI_CLK 5566#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 5667#define GCC_PCIE_PHY_AUX_CLK 5768#define GCC_PCIE_PHY_REFGEN_CLK 5869#define GCC_PCIE_PHY_REFGEN_CLK_SRC 5970#define GCC_PDM2_CLK 6071#define GCC_PDM2_CLK_SRC 6172#define GCC_PDM_AHB_CLK 6273#define GCC_PDM_XO4_CLK 6374#define GCC_PRNG_AHB_CLK 6475#define GCC_QMIP_CAMERA_AHB_CLK 6576#define GCC_QMIP_DISP_AHB_CLK 6677#define GCC_QMIP_VIDEO_AHB_CLK 6778#define GCC_QUPV3_WRAP0_S0_CLK 6879#define GCC_QUPV3_WRAP0_S0_CLK_SRC 6980#define GCC_QUPV3_WRAP0_S1_CLK 7081#define GCC_QUPV3_WRAP0_S1_CLK_SRC 7182#define GCC_QUPV3_WRAP0_S2_CLK 7283#define GCC_QUPV3_WRAP0_S2_CLK_SRC 7384#define GCC_QUPV3_WRAP0_S3_CLK 7485#define GCC_QUPV3_WRAP0_S3_CLK_SRC 7586#define GCC_QUPV3_WRAP0_S4_CLK 7687#define GCC_QUPV3_WRAP0_S4_CLK_SRC 7788#define GCC_QUPV3_WRAP0_S5_CLK 7889#define GCC_QUPV3_WRAP0_S5_CLK_SRC 7990#define GCC_QUPV3_WRAP0_S6_CLK 8091#define GCC_QUPV3_WRAP0_S6_CLK_SRC 8192#define GCC_QUPV3_WRAP0_S7_CLK 8293#define GCC_QUPV3_WRAP0_S7_CLK_SRC 8394#define GCC_QUPV3_WRAP1_S0_CLK 8495#define GCC_QUPV3_WRAP1_S0_CLK_SRC 8596#define GCC_QUPV3_WRAP1_S1_CLK 8697#define GCC_QUPV3_WRAP1_S1_CLK_SRC 8798#define GCC_QUPV3_WRAP1_S2_CLK 8899#define GCC_QUPV3_WRAP1_S2_CLK_SRC 89100#define GCC_QUPV3_WRAP1_S3_CLK 90101#define GCC_QUPV3_WRAP1_S3_CLK_SRC 91102#define GCC_QUPV3_WRAP1_S4_CLK 92103#define GCC_QUPV3_WRAP1_S4_CLK_SRC 93104#define GCC_QUPV3_WRAP1_S5_CLK 94105#define GCC_QUPV3_WRAP1_S5_CLK_SRC 95106#define GCC_QUPV3_WRAP1_S6_CLK 96107#define GCC_QUPV3_WRAP1_S6_CLK_SRC 97108#define GCC_QUPV3_WRAP1_S7_CLK 98109#define GCC_QUPV3_WRAP1_S7_CLK_SRC 99110#define GCC_QUPV3_WRAP_0_M_AHB_CLK 100111#define GCC_QUPV3_WRAP_0_S_AHB_CLK 101112#define GCC_QUPV3_WRAP_1_M_AHB_CLK 102113#define GCC_QUPV3_WRAP_1_S_AHB_CLK 103114#define GCC_SDCC2_AHB_CLK 104115#define GCC_SDCC2_APPS_CLK 105116#define GCC_SDCC2_APPS_CLK_SRC 106117#define GCC_SDCC4_AHB_CLK 107118#define GCC_SDCC4_APPS_CLK 108119#define GCC_SDCC4_APPS_CLK_SRC 109120#define GCC_SYS_NOC_CPUSS_AHB_CLK 110121#define GCC_TSIF_AHB_CLK 111122#define GCC_TSIF_INACTIVITY_TIMERS_CLK 112123#define GCC_TSIF_REF_CLK 113124#define GCC_TSIF_REF_CLK_SRC 114125#define GCC_UFS_CARD_AHB_CLK 115126#define GCC_UFS_CARD_AXI_CLK 116127#define GCC_UFS_CARD_AXI_CLK_SRC 117128#define GCC_UFS_CARD_CLKREF_CLK 118129#define GCC_UFS_CARD_ICE_CORE_CLK 119130#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120131#define GCC_UFS_CARD_PHY_AUX_CLK 121132#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122133#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123134#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124135#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125136#define GCC_UFS_CARD_UNIPRO_CORE_CLK 126137#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127138#define GCC_UFS_MEM_CLKREF_CLK 128139#define GCC_UFS_PHY_AHB_CLK 129140#define GCC_UFS_PHY_AXI_CLK 130141#define GCC_UFS_PHY_AXI_CLK_SRC 131142#define GCC_UFS_PHY_ICE_CORE_CLK 132143#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133144#define GCC_UFS_PHY_PHY_AUX_CLK 134145#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135146#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136147#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137148#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138149#define GCC_UFS_PHY_UNIPRO_CORE_CLK 139150#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140151#define GCC_USB30_PRIM_MASTER_CLK 141152#define GCC_USB30_PRIM_MASTER_CLK_SRC 142153#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143154#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144155#define GCC_USB30_PRIM_SLEEP_CLK 145156#define GCC_USB30_SEC_MASTER_CLK 146157#define GCC_USB30_SEC_MASTER_CLK_SRC 147158#define GCC_USB30_SEC_MOCK_UTMI_CLK 148159#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149160#define GCC_USB30_SEC_SLEEP_CLK 150161#define GCC_USB3_PRIM_CLKREF_CLK 151162#define GCC_USB3_PRIM_PHY_AUX_CLK 152163#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153164#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154165#define GCC_USB3_PRIM_PHY_PIPE_CLK 155166#define GCC_USB3_SEC_CLKREF_CLK 156167#define GCC_USB3_SEC_PHY_AUX_CLK 157168#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158169#define GCC_USB3_SEC_PHY_PIPE_CLK 159170#define GCC_USB3_SEC_PHY_COM_AUX_CLK 160171#define GCC_USB_PHY_CFG_AHB2PHY_CLK 161172#define GCC_VIDEO_AHB_CLK 162173#define GCC_VIDEO_AXI_CLK 163174#define GCC_VIDEO_XO_CLK 164175#define GPLL0 165176#define GPLL0_OUT_EVEN 166177#define GPLL0_OUT_MAIN 167178#define GCC_GPU_IREF_CLK 168179#define GCC_SDCC1_AHB_CLK 169180#define GCC_SDCC1_APPS_CLK 170181#define GCC_SDCC1_ICE_CORE_CLK 171182#define GCC_SDCC1_APPS_CLK_SRC 172183#define GCC_SDCC1_ICE_CORE_CLK_SRC 173184#define GCC_APC_VS_CLK 174185#define GCC_GPU_VS_CLK 175186#define GCC_MSS_VS_CLK 176187#define GCC_VDDA_VS_CLK 177188#define GCC_VDDCX_VS_CLK 178189#define GCC_VDDMX_VS_CLK 179190#define GCC_VS_CTRL_AHB_CLK 180191#define GCC_VS_CTRL_CLK 181192#define GCC_VS_CTRL_CLK_SRC 182193#define GCC_VSENSOR_CLK_SRC 183194#define GPLL4 184195#define GCC_CPUSS_DVM_BUS_CLK 185196#define GCC_CPUSS_GNOC_CLK 186197#define GCC_QSPI_CORE_CLK_SRC 187198#define GCC_QSPI_CORE_CLK 188199#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189200#define GCC_LPASS_Q6_AXI_CLK 190201#define GCC_LPASS_SWAY_CLK 191202#define GPLL6 192203 204/* GCC Resets */205#define GCC_MMSS_BCR 0206#define GCC_PCIE_0_BCR 1207#define GCC_PCIE_1_BCR 2208#define GCC_PCIE_PHY_BCR 3209#define GCC_PDM_BCR 4210#define GCC_PRNG_BCR 5211#define GCC_QUPV3_WRAPPER_0_BCR 6212#define GCC_QUPV3_WRAPPER_1_BCR 7213#define GCC_QUSB2PHY_PRIM_BCR 8214#define GCC_QUSB2PHY_SEC_BCR 9215#define GCC_SDCC2_BCR 10216#define GCC_SDCC4_BCR 11217#define GCC_TSIF_BCR 12218#define GCC_UFS_CARD_BCR 13219#define GCC_UFS_PHY_BCR 14220#define GCC_USB30_PRIM_BCR 15221#define GCC_USB30_SEC_BCR 16222#define GCC_USB3_PHY_PRIM_BCR 17223#define GCC_USB3PHY_PHY_PRIM_BCR 18224#define GCC_USB3_DP_PHY_PRIM_BCR 19225#define GCC_USB3_PHY_SEC_BCR 20226#define GCC_USB3PHY_PHY_SEC_BCR 21227#define GCC_USB3_DP_PHY_SEC_BCR 22228#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23229#define GCC_PCIE_0_PHY_BCR 24230#define GCC_PCIE_1_PHY_BCR 25231 232/* GCC GDSCRs */233#define PCIE_0_GDSC 0234#define PCIE_1_GDSC 1235#define UFS_CARD_GDSC 2236#define UFS_PHY_GDSC 3237#define USB30_PRIM_GDSC 4238#define USB30_SEC_GDSC 5239#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6240#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7241#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8242#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9243#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10244#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11245#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12246 247#endif248