118 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.4 * Copyright (c) 2020, Linaro Ltd.5 */6 7#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX55_H8#define _DT_BINDINGS_CLK_QCOM_GCC_SDX55_H9 10#define GPLL0 311#define GPLL0_OUT_EVEN 412#define GPLL4 513#define GPLL4_OUT_EVEN 614#define GPLL5 715#define GCC_AHB_PCIE_LINK_CLK 816#define GCC_BLSP1_AHB_CLK 917#define GCC_BLSP1_QUP1_I2C_APPS_CLK 1018#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 1119#define GCC_BLSP1_QUP1_SPI_APPS_CLK 1220#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 1321#define GCC_BLSP1_QUP2_I2C_APPS_CLK 1422#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 1523#define GCC_BLSP1_QUP2_SPI_APPS_CLK 1624#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 1725#define GCC_BLSP1_QUP3_I2C_APPS_CLK 1826#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 1927#define GCC_BLSP1_QUP3_SPI_APPS_CLK 2028#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 2129#define GCC_BLSP1_QUP4_I2C_APPS_CLK 2230#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 2331#define GCC_BLSP1_QUP4_SPI_APPS_CLK 2432#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 2533#define GCC_BLSP1_UART1_APPS_CLK 2634#define GCC_BLSP1_UART1_APPS_CLK_SRC 2735#define GCC_BLSP1_UART2_APPS_CLK 2836#define GCC_BLSP1_UART2_APPS_CLK_SRC 2937#define GCC_BLSP1_UART3_APPS_CLK 3038#define GCC_BLSP1_UART3_APPS_CLK_SRC 3139#define GCC_BLSP1_UART4_APPS_CLK 3240#define GCC_BLSP1_UART4_APPS_CLK_SRC 3341#define GCC_BOOT_ROM_AHB_CLK 3442#define GCC_CE1_AHB_CLK 3543#define GCC_CE1_AXI_CLK 3644#define GCC_CE1_CLK 3745#define GCC_CPUSS_AHB_CLK 3846#define GCC_CPUSS_AHB_CLK_SRC 3947#define GCC_CPUSS_GNOC_CLK 4048#define GCC_CPUSS_RBCPR_CLK 4149#define GCC_CPUSS_RBCPR_CLK_SRC 4250#define GCC_EMAC_CLK_SRC 4351#define GCC_EMAC_PTP_CLK_SRC 4452#define GCC_ETH_AXI_CLK 4553#define GCC_ETH_PTP_CLK 4654#define GCC_ETH_RGMII_CLK 4755#define GCC_ETH_SLAVE_AHB_CLK 4856#define GCC_GP1_CLK 4957#define GCC_GP1_CLK_SRC 5058#define GCC_GP2_CLK 5159#define GCC_GP2_CLK_SRC 5260#define GCC_GP3_CLK 5361#define GCC_GP3_CLK_SRC 5462#define GCC_PCIE_0_CLKREF_CLK 5563#define GCC_PCIE_AUX_CLK 5664#define GCC_PCIE_AUX_PHY_CLK_SRC 5765#define GCC_PCIE_CFG_AHB_CLK 5866#define GCC_PCIE_MSTR_AXI_CLK 5967#define GCC_PCIE_PIPE_CLK 6068#define GCC_PCIE_RCHNG_PHY_CLK 6169#define GCC_PCIE_RCHNG_PHY_CLK_SRC 6270#define GCC_PCIE_SLEEP_CLK 6371#define GCC_PCIE_SLV_AXI_CLK 6472#define GCC_PCIE_SLV_Q2A_AXI_CLK 6573#define GCC_PDM2_CLK 6674#define GCC_PDM2_CLK_SRC 6775#define GCC_PDM_AHB_CLK 6876#define GCC_PDM_XO4_CLK 6977#define GCC_SDCC1_AHB_CLK 7078#define GCC_SDCC1_APPS_CLK 7179#define GCC_SDCC1_APPS_CLK_SRC 7280#define GCC_SYS_NOC_CPUSS_AHB_CLK 7381#define GCC_USB30_MASTER_CLK 7482#define GCC_USB30_MASTER_CLK_SRC 7583#define GCC_USB30_MOCK_UTMI_CLK 7684#define GCC_USB30_MOCK_UTMI_CLK_SRC 7785#define GCC_USB30_MSTR_AXI_CLK 7886#define GCC_USB30_SLEEP_CLK 7987#define GCC_USB30_SLV_AHB_CLK 8088#define GCC_USB3_PHY_AUX_CLK 8189#define GCC_USB3_PHY_AUX_CLK_SRC 8290#define GCC_USB3_PHY_PIPE_CLK 8391#define GCC_USB3_PRIM_CLKREF_CLK 8492#define GCC_USB_PHY_CFG_AHB2PHY_CLK 8593#define GCC_XO_DIV4_CLK 8694#define GCC_XO_PCIE_LINK_CLK 8795 96#define GCC_EMAC_BCR 097#define GCC_PCIE_BCR 198#define GCC_PCIE_LINK_DOWN_BCR 299#define GCC_PCIE_NOCSR_COM_PHY_BCR 3100#define GCC_PCIE_PHY_BCR 4101#define GCC_PCIE_PHY_CFG_AHB_BCR 5102#define GCC_PCIE_PHY_COM_BCR 6103#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 7104#define GCC_PDM_BCR 8105#define GCC_QUSB2PHY_BCR 9106#define GCC_TCSR_PCIE_BCR 10107#define GCC_USB30_BCR 11108#define GCC_USB3_PHY_BCR 12109#define GCC_USB3PHY_PHY_BCR 13110#define GCC_USB_PHY_CFG_AHB2PHY_BCR 14111 112/* GCC power domains */113#define USB30_GDSC 0114#define PCIE_GDSC 1115#define EMAC_GDSC 2116 117#endif118