179 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.4 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>5 */6 7#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6350_H8#define _DT_BINDINGS_CLK_QCOM_GCC_SM6350_H9 10/* GCC clocks */11#define GPLL0 012#define GPLL0_OUT_EVEN 113#define GPLL0_OUT_ODD 214#define GPLL6 315#define GPLL6_OUT_EVEN 416#define GPLL7 517#define GCC_AGGRE_CNOC_PERIPH_CENTER_AHB_CLK 618#define GCC_AGGRE_NOC_CENTER_AHB_CLK 719#define GCC_AGGRE_NOC_PCIE_SF_AXI_CLK 820#define GCC_AGGRE_NOC_PCIE_TBU_CLK 921#define GCC_AGGRE_NOC_WLAN_AXI_CLK 1022#define GCC_AGGRE_UFS_PHY_AXI_CLK 1123#define GCC_AGGRE_USB3_PRIM_AXI_CLK 1224#define GCC_BOOT_ROM_AHB_CLK 1325#define GCC_CAMERA_AHB_CLK 1426#define GCC_CAMERA_AXI_CLK 1527#define GCC_CAMERA_THROTTLE_NRT_AXI_CLK 1628#define GCC_CAMERA_THROTTLE_RT_AXI_CLK 1729#define GCC_CAMERA_XO_CLK 1830#define GCC_CE1_AHB_CLK 1931#define GCC_CE1_AXI_CLK 2032#define GCC_CE1_CLK 2133#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 2234#define GCC_CPUSS_AHB_CLK 2335#define GCC_CPUSS_AHB_CLK_SRC 2436#define GCC_CPUSS_AHB_DIV_CLK_SRC 2537#define GCC_CPUSS_GNOC_CLK 2638#define GCC_CPUSS_RBCPR_CLK 2739#define GCC_DDRSS_GPU_AXI_CLK 2840#define GCC_DISP_AHB_CLK 2941#define GCC_DISP_AXI_CLK 3042#define GCC_DISP_CC_SLEEP_CLK 3143#define GCC_DISP_CC_XO_CLK 3244#define GCC_DISP_GPLL0_CLK 3345#define GCC_DISP_THROTTLE_AXI_CLK 3446#define GCC_DISP_XO_CLK 3547#define GCC_GP1_CLK 3648#define GCC_GP1_CLK_SRC 3749#define GCC_GP2_CLK 3850#define GCC_GP2_CLK_SRC 3951#define GCC_GP3_CLK 4052#define GCC_GP3_CLK_SRC 4153#define GCC_GPU_CFG_AHB_CLK 4254#define GCC_GPU_GPLL0_CLK 4355#define GCC_GPU_GPLL0_DIV_CLK 4456#define GCC_GPU_MEMNOC_GFX_CLK 4557#define GCC_GPU_SNOC_DVM_GFX_CLK 4658#define GCC_NPU_AXI_CLK 4759#define GCC_NPU_BWMON_AXI_CLK 4860#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 4961#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 5062#define GCC_NPU_CFG_AHB_CLK 5163#define GCC_NPU_DMA_CLK 5264#define GCC_NPU_GPLL0_CLK 5365#define GCC_NPU_GPLL0_DIV_CLK 5466#define GCC_PCIE_0_AUX_CLK 5567#define GCC_PCIE_0_AUX_CLK_SRC 5668#define GCC_PCIE_0_CFG_AHB_CLK 5769#define GCC_PCIE_0_MSTR_AXI_CLK 5870#define GCC_PCIE_0_PIPE_CLK 5971#define GCC_PCIE_0_SLV_AXI_CLK 6072#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 6173#define GCC_PCIE_PHY_RCHNG_CLK 6274#define GCC_PCIE_PHY_RCHNG_CLK_SRC 6375#define GCC_PDM2_CLK 6476#define GCC_PDM2_CLK_SRC 6577#define GCC_PDM_AHB_CLK 6678#define GCC_PDM_XO4_CLK 6779#define GCC_PRNG_AHB_CLK 6880#define GCC_QUPV3_WRAP0_CORE_2X_CLK 6981#define GCC_QUPV3_WRAP0_CORE_CLK 7082#define GCC_QUPV3_WRAP0_S0_CLK 7183#define GCC_QUPV3_WRAP0_S0_CLK_SRC 7284#define GCC_QUPV3_WRAP0_S1_CLK 7385#define GCC_QUPV3_WRAP0_S1_CLK_SRC 7486#define GCC_QUPV3_WRAP0_S2_CLK 7587#define GCC_QUPV3_WRAP0_S2_CLK_SRC 7688#define GCC_QUPV3_WRAP0_S3_CLK 7789#define GCC_QUPV3_WRAP0_S3_CLK_SRC 7890#define GCC_QUPV3_WRAP0_S4_CLK 7991#define GCC_QUPV3_WRAP0_S4_CLK_SRC 8092#define GCC_QUPV3_WRAP0_S5_CLK 8193#define GCC_QUPV3_WRAP0_S5_CLK_SRC 8294#define GCC_QUPV3_WRAP1_CORE_2X_CLK 8395#define GCC_QUPV3_WRAP1_CORE_CLK 8496#define GCC_QUPV3_WRAP1_S0_CLK 8597#define GCC_QUPV3_WRAP1_S0_CLK_SRC 8698#define GCC_QUPV3_WRAP1_S1_CLK 8799#define GCC_QUPV3_WRAP1_S1_CLK_SRC 88100#define GCC_QUPV3_WRAP1_S2_CLK 89101#define GCC_QUPV3_WRAP1_S2_CLK_SRC 90102#define GCC_QUPV3_WRAP1_S3_CLK 91103#define GCC_QUPV3_WRAP1_S3_CLK_SRC 92104#define GCC_QUPV3_WRAP1_S4_CLK 93105#define GCC_QUPV3_WRAP1_S4_CLK_SRC 94106#define GCC_QUPV3_WRAP1_S5_CLK 95107#define GCC_QUPV3_WRAP1_S5_CLK_SRC 96108#define GCC_QUPV3_WRAP_0_M_AHB_CLK 97109#define GCC_QUPV3_WRAP_0_S_AHB_CLK 98110#define GCC_QUPV3_WRAP_1_M_AHB_CLK 99111#define GCC_QUPV3_WRAP_1_S_AHB_CLK 100112#define GCC_SDCC1_AHB_CLK 101113#define GCC_SDCC1_APPS_CLK 102114#define GCC_SDCC1_APPS_CLK_SRC 103115#define GCC_SDCC1_ICE_CORE_CLK 104116#define GCC_SDCC1_ICE_CORE_CLK_SRC 105117#define GCC_SDCC2_AHB_CLK 106118#define GCC_SDCC2_APPS_CLK 107119#define GCC_SDCC2_APPS_CLK_SRC 108120#define GCC_SYS_NOC_CPUSS_AHB_CLK 109121#define GCC_UFS_MEM_CLKREF_CLK 110122#define GCC_UFS_PHY_AHB_CLK 111123#define GCC_UFS_PHY_AXI_CLK 112124#define GCC_UFS_PHY_AXI_CLK_SRC 113125#define GCC_UFS_PHY_ICE_CORE_CLK 114126#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 115127#define GCC_UFS_PHY_PHY_AUX_CLK 116128#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 117129#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 118130#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 119131#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 120132#define GCC_UFS_PHY_UNIPRO_CORE_CLK 121133#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 122134#define GCC_USB30_PRIM_MASTER_CLK 123135#define GCC_USB30_PRIM_MASTER_CLK_SRC 124136#define GCC_USB30_PRIM_MOCK_UTMI_CLK 125137#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 126138#define GCC_USB30_PRIM_MOCK_UTMI_DIV_CLK_SRC 127139#define GCC_USB3_PRIM_CLKREF_CLK 128140#define GCC_USB30_PRIM_SLEEP_CLK 129141#define GCC_USB3_PRIM_PHY_AUX_CLK 130142#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 131143#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 132144#define GCC_USB3_PRIM_PHY_PIPE_CLK 133145#define GCC_VIDEO_AHB_CLK 134146#define GCC_VIDEO_AXI_CLK 135147#define GCC_VIDEO_THROTTLE_AXI_CLK 136148#define GCC_VIDEO_XO_CLK 137149#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 138150#define GCC_UFS_PHY_AXI_HW_CTL_CLK 139151#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 140152#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 141153#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 142154#define GCC_RX5_PCIE_CLKREF_CLK 143155#define GCC_GPU_GPLL0_MAIN_DIV_CLK_SRC 144156#define GCC_NPU_PLL0_MAIN_DIV_CLK_SRC 145157 158/* GCC resets */159#define GCC_QUSB2PHY_PRIM_BCR 0160#define GCC_QUSB2PHY_SEC_BCR 1161#define GCC_SDCC1_BCR 2162#define GCC_SDCC2_BCR 3163#define GCC_UFS_PHY_BCR 4164#define GCC_USB30_PRIM_BCR 5165#define GCC_PCIE_0_BCR 6166#define GCC_PCIE_0_PHY_BCR 7167#define GCC_QUPV3_WRAPPER_0_BCR 8168#define GCC_QUPV3_WRAPPER_1_BCR 9169#define GCC_USB3_PHY_PRIM_BCR 10170#define GCC_USB3_DP_PHY_PRIM_BCR 11171 172/* GCC GDSCs */173#define USB30_PRIM_GDSC 0174#define UFS_PHY_GDSC 1175#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2176#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 3177 178#endif179