266 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.4 * Copyright (c) 2020-2021, Linaro Limited5 */6 7#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H8#define _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H9 10/* GCC HW clocks */11#define PCIE_0_PIPE_CLK 112#define PCIE_1_PIPE_CLK 213#define UFS_CARD_RX_SYMBOL_0_CLK 314#define UFS_CARD_RX_SYMBOL_1_CLK 415#define UFS_CARD_TX_SYMBOL_0_CLK 516#define UFS_PHY_RX_SYMBOL_0_CLK 617#define UFS_PHY_RX_SYMBOL_1_CLK 718#define UFS_PHY_TX_SYMBOL_0_CLK 819#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 920#define USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK 1021 22/* GCC clocks */23#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 1124#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 1225#define GCC_AGGRE_NOC_PCIE_TBU_CLK 1326#define GCC_AGGRE_UFS_CARD_AXI_CLK 1427#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 1528#define GCC_AGGRE_UFS_PHY_AXI_CLK 1629#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 1730#define GCC_AGGRE_USB3_PRIM_AXI_CLK 1831#define GCC_AGGRE_USB3_SEC_AXI_CLK 1932#define GCC_BOOT_ROM_AHB_CLK 2033#define GCC_CAMERA_HF_AXI_CLK 2134#define GCC_CAMERA_SF_AXI_CLK 2235#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 2336#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 2437#define GCC_DDRSS_GPU_AXI_CLK 2538#define GCC_DDRSS_PCIE_SF_TBU_CLK 2639#define GCC_DISP_HF_AXI_CLK 2740#define GCC_DISP_SF_AXI_CLK 2841#define GCC_GP1_CLK 2942#define GCC_GP1_CLK_SRC 3043#define GCC_GP2_CLK 3144#define GCC_GP2_CLK_SRC 3245#define GCC_GP3_CLK 3346#define GCC_GP3_CLK_SRC 3447#define GCC_GPLL0 3548#define GCC_GPLL0_OUT_EVEN 3649#define GCC_GPLL4 3750#define GCC_GPLL9 3851#define GCC_GPU_GPLL0_CLK_SRC 3952#define GCC_GPU_GPLL0_DIV_CLK_SRC 4053#define GCC_GPU_IREF_EN 4154#define GCC_GPU_MEMNOC_GFX_CLK 4255#define GCC_GPU_SNOC_DVM_GFX_CLK 4356#define GCC_PCIE0_PHY_RCHNG_CLK 4457#define GCC_PCIE1_PHY_RCHNG_CLK 4558#define GCC_PCIE_0_AUX_CLK 4659#define GCC_PCIE_0_AUX_CLK_SRC 4760#define GCC_PCIE_0_CFG_AHB_CLK 4861#define GCC_PCIE_0_CLKREF_EN 4962#define GCC_PCIE_0_MSTR_AXI_CLK 5063#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 5164#define GCC_PCIE_0_PIPE_CLK 5265#define GCC_PCIE_0_PIPE_CLK_SRC 5366#define GCC_PCIE_0_SLV_AXI_CLK 5467#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 5568#define GCC_PCIE_1_AUX_CLK 5669#define GCC_PCIE_1_AUX_CLK_SRC 5770#define GCC_PCIE_1_CFG_AHB_CLK 5871#define GCC_PCIE_1_CLKREF_EN 5972#define GCC_PCIE_1_MSTR_AXI_CLK 6073#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 6174#define GCC_PCIE_1_PIPE_CLK 6275#define GCC_PCIE_1_PIPE_CLK_SRC 6376#define GCC_PCIE_1_SLV_AXI_CLK 6477#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 6578#define GCC_PDM2_CLK 6679#define GCC_PDM2_CLK_SRC 6780#define GCC_PDM_AHB_CLK 6881#define GCC_PDM_XO4_CLK 6982#define GCC_QMIP_CAMERA_NRT_AHB_CLK 7083#define GCC_QMIP_CAMERA_RT_AHB_CLK 7184#define GCC_QMIP_DISP_AHB_CLK 7285#define GCC_QMIP_VIDEO_CVP_AHB_CLK 7386#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 7487#define GCC_QUPV3_WRAP0_CORE_2X_CLK 7588#define GCC_QUPV3_WRAP0_CORE_CLK 7689#define GCC_QUPV3_WRAP0_S0_CLK 7790#define GCC_QUPV3_WRAP0_S0_CLK_SRC 7891#define GCC_QUPV3_WRAP0_S1_CLK 7992#define GCC_QUPV3_WRAP0_S1_CLK_SRC 8093#define GCC_QUPV3_WRAP0_S2_CLK 8194#define GCC_QUPV3_WRAP0_S2_CLK_SRC 8295#define GCC_QUPV3_WRAP0_S3_CLK 8396#define GCC_QUPV3_WRAP0_S3_CLK_SRC 8497#define GCC_QUPV3_WRAP0_S4_CLK 8598#define GCC_QUPV3_WRAP0_S4_CLK_SRC 8699#define GCC_QUPV3_WRAP0_S5_CLK 87100#define GCC_QUPV3_WRAP0_S5_CLK_SRC 88101#define GCC_QUPV3_WRAP0_S6_CLK 89102#define GCC_QUPV3_WRAP0_S6_CLK_SRC 90103#define GCC_QUPV3_WRAP0_S7_CLK 91104#define GCC_QUPV3_WRAP0_S7_CLK_SRC 92105#define GCC_QUPV3_WRAP1_CORE_2X_CLK 93106#define GCC_QUPV3_WRAP1_CORE_CLK 94107#define GCC_QUPV3_WRAP1_S0_CLK 95108#define GCC_QUPV3_WRAP1_S0_CLK_SRC 96109#define GCC_QUPV3_WRAP1_S1_CLK 97110#define GCC_QUPV3_WRAP1_S1_CLK_SRC 98111#define GCC_QUPV3_WRAP1_S2_CLK 99112#define GCC_QUPV3_WRAP1_S2_CLK_SRC 100113#define GCC_QUPV3_WRAP1_S3_CLK 101114#define GCC_QUPV3_WRAP1_S3_CLK_SRC 102115#define GCC_QUPV3_WRAP1_S4_CLK 103116#define GCC_QUPV3_WRAP1_S4_CLK_SRC 104117#define GCC_QUPV3_WRAP1_S5_CLK 105118#define GCC_QUPV3_WRAP1_S5_CLK_SRC 106119#define GCC_QUPV3_WRAP2_CORE_2X_CLK 107120#define GCC_QUPV3_WRAP2_CORE_CLK 108121#define GCC_QUPV3_WRAP2_S0_CLK 109122#define GCC_QUPV3_WRAP2_S0_CLK_SRC 110123#define GCC_QUPV3_WRAP2_S1_CLK 111124#define GCC_QUPV3_WRAP2_S1_CLK_SRC 112125#define GCC_QUPV3_WRAP2_S2_CLK 113126#define GCC_QUPV3_WRAP2_S2_CLK_SRC 114127#define GCC_QUPV3_WRAP2_S3_CLK 115128#define GCC_QUPV3_WRAP2_S3_CLK_SRC 116129#define GCC_QUPV3_WRAP2_S4_CLK 117130#define GCC_QUPV3_WRAP2_S4_CLK_SRC 118131#define GCC_QUPV3_WRAP2_S5_CLK 119132#define GCC_QUPV3_WRAP2_S5_CLK_SRC 120133#define GCC_QUPV3_WRAP_0_M_AHB_CLK 121134#define GCC_QUPV3_WRAP_0_S_AHB_CLK 122135#define GCC_QUPV3_WRAP_1_M_AHB_CLK 123136#define GCC_QUPV3_WRAP_1_S_AHB_CLK 124137#define GCC_QUPV3_WRAP_2_M_AHB_CLK 125138#define GCC_QUPV3_WRAP_2_S_AHB_CLK 126139#define GCC_SDCC2_AHB_CLK 127140#define GCC_SDCC2_APPS_CLK 128141#define GCC_SDCC2_APPS_CLK_SRC 129142#define GCC_SDCC4_AHB_CLK 130143#define GCC_SDCC4_APPS_CLK 131144#define GCC_SDCC4_APPS_CLK_SRC 132145#define GCC_THROTTLE_PCIE_AHB_CLK 133146#define GCC_UFS_1_CLKREF_EN 134147#define GCC_UFS_CARD_AHB_CLK 135148#define GCC_UFS_CARD_AXI_CLK 136149#define GCC_UFS_CARD_AXI_CLK_SRC 137150#define GCC_UFS_CARD_AXI_HW_CTL_CLK 138151#define GCC_UFS_CARD_ICE_CORE_CLK 139152#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 140153#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 141154#define GCC_UFS_CARD_PHY_AUX_CLK 142155#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 143156#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 144157#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 145158#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 146159#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 147160#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 148161#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 149162#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 150163#define GCC_UFS_CARD_UNIPRO_CORE_CLK 151164#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 152165#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 153166#define GCC_UFS_PHY_AHB_CLK 154167#define GCC_UFS_PHY_AXI_CLK 155168#define GCC_UFS_PHY_AXI_CLK_SRC 156169#define GCC_UFS_PHY_AXI_HW_CTL_CLK 157170#define GCC_UFS_PHY_ICE_CORE_CLK 158171#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 159172#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 160173#define GCC_UFS_PHY_PHY_AUX_CLK 161174#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 162175#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 163176#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 164177#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 165178#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 166179#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 167180#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168181#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 169182#define GCC_UFS_PHY_UNIPRO_CORE_CLK 170183#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 171184#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 172185#define GCC_USB30_PRIM_MASTER_CLK 173186#define GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON 174187#define GCC_USB30_PRIM_MASTER_CLK_SRC 175188#define GCC_USB30_PRIM_MOCK_UTMI_CLK 176189#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 177190#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 178191#define GCC_USB30_PRIM_SLEEP_CLK 179192#define GCC_USB30_SEC_MASTER_CLK 180193#define GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON 181194#define GCC_USB30_SEC_MASTER_CLK_SRC 182195#define GCC_USB30_SEC_MOCK_UTMI_CLK 183196#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 184197#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 185198#define GCC_USB30_SEC_SLEEP_CLK 186199#define GCC_USB3_PRIM_PHY_AUX_CLK 187200#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 188201#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 189202#define GCC_USB3_PRIM_PHY_PIPE_CLK 190203#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 191204#define GCC_USB3_SEC_CLKREF_EN 192205#define GCC_USB3_SEC_PHY_AUX_CLK 193206#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 194207#define GCC_USB3_SEC_PHY_COM_AUX_CLK 195208#define GCC_USB3_SEC_PHY_PIPE_CLK 196209#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 197210#define GCC_VIDEO_AXI0_CLK 198211#define GCC_VIDEO_AXI1_CLK 199212 213/* GCC resets */214#define GCC_CAMERA_BCR 0215#define GCC_DISPLAY_BCR 1216#define GCC_GPU_BCR 2217#define GCC_MMSS_BCR 3218#define GCC_PCIE_0_BCR 4219#define GCC_PCIE_0_LINK_DOWN_BCR 5220#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6221#define GCC_PCIE_0_PHY_BCR 7222#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8223#define GCC_PCIE_1_BCR 9224#define GCC_PCIE_1_LINK_DOWN_BCR 10225#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11226#define GCC_PCIE_1_PHY_BCR 12227#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13228#define GCC_PCIE_PHY_CFG_AHB_BCR 14229#define GCC_PCIE_PHY_COM_BCR 15230#define GCC_PDM_BCR 16231#define GCC_QUPV3_WRAPPER_0_BCR 17232#define GCC_QUPV3_WRAPPER_1_BCR 18233#define GCC_QUPV3_WRAPPER_2_BCR 19234#define GCC_QUSB2PHY_PRIM_BCR 20235#define GCC_QUSB2PHY_SEC_BCR 21236#define GCC_SDCC2_BCR 22237#define GCC_SDCC4_BCR 23238#define GCC_UFS_CARD_BCR 24239#define GCC_UFS_PHY_BCR 25240#define GCC_USB30_PRIM_BCR 26241#define GCC_USB30_SEC_BCR 27242#define GCC_USB3_DP_PHY_PRIM_BCR 28243#define GCC_USB3_DP_PHY_SEC_BCR 29244#define GCC_USB3_PHY_PRIM_BCR 30245#define GCC_USB3_PHY_SEC_BCR 31246#define GCC_USB3PHY_PHY_PRIM_BCR 32247#define GCC_USB3PHY_PHY_SEC_BCR 33248#define GCC_USB_PHY_CFG_AHB2PHY_BCR 34249#define GCC_VIDEO_AXI0_CLK_ARES 35250#define GCC_VIDEO_AXI1_CLK_ARES 36251#define GCC_VIDEO_BCR 37252 253/* GCC power domains */254#define PCIE_0_GDSC 0255#define PCIE_1_GDSC 1256#define UFS_CARD_GDSC 2257#define UFS_PHY_GDSC 3258#define USB30_PRIM_GDSC 4259#define USB30_SEC_GDSC 5260#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 6261#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 7262#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 8263#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 9264 265#endif266