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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.4 */5 6#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8998_H7#define _DT_BINDINGS_CLK_MSM_MMCC_8998_H8 9#define MMPLL0 010#define MMPLL0_OUT_EVEN 111#define MMPLL1 212#define MMPLL1_OUT_EVEN 313#define MMPLL3 414#define MMPLL3_OUT_EVEN 515#define MMPLL4 616#define MMPLL4_OUT_EVEN 717#define MMPLL5 818#define MMPLL5_OUT_EVEN 919#define MMPLL6 1020#define MMPLL6_OUT_EVEN 1121#define MMPLL7 1222#define MMPLL7_OUT_EVEN 1323#define MMPLL10 1424#define MMPLL10_OUT_EVEN 1525#define BYTE0_CLK_SRC 1626#define BYTE1_CLK_SRC 1727#define CCI_CLK_SRC 1828#define CPP_CLK_SRC 1929#define CSI0_CLK_SRC 2030#define CSI1_CLK_SRC 2131#define CSI2_CLK_SRC 2232#define CSI3_CLK_SRC 2333#define CSIPHY_CLK_SRC 2434#define CSI0PHYTIMER_CLK_SRC 2535#define CSI1PHYTIMER_CLK_SRC 2636#define CSI2PHYTIMER_CLK_SRC 2737#define DP_AUX_CLK_SRC 2838#define DP_CRYPTO_CLK_SRC 2939#define DP_LINK_CLK_SRC 3040#define DP_PIXEL_CLK_SRC 3141#define ESC0_CLK_SRC 3242#define ESC1_CLK_SRC 3343#define EXTPCLK_CLK_SRC 3444#define FD_CORE_CLK_SRC 3545#define HDMI_CLK_SRC 3646#define JPEG0_CLK_SRC 3747#define MAXI_CLK_SRC 3848#define MCLK0_CLK_SRC 3949#define MCLK1_CLK_SRC 4050#define MCLK2_CLK_SRC 4151#define MCLK3_CLK_SRC 4252#define MDP_CLK_SRC 4353#define VSYNC_CLK_SRC 4454#define AHB_CLK_SRC 4555#define AXI_CLK_SRC 4656#define PCLK0_CLK_SRC 4757#define PCLK1_CLK_SRC 4858#define ROT_CLK_SRC 4959#define VIDEO_CORE_CLK_SRC 5060#define VIDEO_SUBCORE0_CLK_SRC 5161#define VIDEO_SUBCORE1_CLK_SRC 5262#define VFE0_CLK_SRC 5363#define VFE1_CLK_SRC 5464#define MISC_AHB_CLK 5565#define VIDEO_CORE_CLK 5666#define VIDEO_AHB_CLK 5767#define VIDEO_AXI_CLK 5868#define VIDEO_MAXI_CLK 5969#define VIDEO_SUBCORE0_CLK 6070#define VIDEO_SUBCORE1_CLK 6171#define MDSS_AHB_CLK 6272#define MDSS_HDMI_DP_AHB_CLK 6373#define MDSS_AXI_CLK 6474#define MDSS_PCLK0_CLK 6575#define MDSS_PCLK1_CLK 6676#define MDSS_MDP_CLK 6777#define MDSS_MDP_LUT_CLK 6878#define MDSS_EXTPCLK_CLK 6979#define MDSS_VSYNC_CLK 7080#define MDSS_HDMI_CLK 7181#define MDSS_BYTE0_CLK 7282#define MDSS_BYTE1_CLK 7383#define MDSS_ESC0_CLK 7484#define MDSS_ESC1_CLK 7585#define MDSS_ROT_CLK 7686#define MDSS_DP_LINK_CLK 7787#define MDSS_DP_LINK_INTF_CLK 7888#define MDSS_DP_CRYPTO_CLK 7989#define MDSS_DP_PIXEL_CLK 8090#define MDSS_DP_AUX_CLK 8191#define MDSS_BYTE0_INTF_CLK 8292#define MDSS_BYTE1_INTF_CLK 8393#define CAMSS_CSI0PHYTIMER_CLK 8494#define CAMSS_CSI1PHYTIMER_CLK 8595#define CAMSS_CSI2PHYTIMER_CLK 8696#define CAMSS_CSI0_CLK 8797#define CAMSS_CSI0_AHB_CLK 8898#define CAMSS_CSI0RDI_CLK 8999#define CAMSS_CSI0PIX_CLK 90100#define CAMSS_CSI1_CLK 91101#define CAMSS_CSI1_AHB_CLK 92102#define CAMSS_CSI1RDI_CLK 93103#define CAMSS_CSI1PIX_CLK 94104#define CAMSS_CSI2_CLK 95105#define CAMSS_CSI2_AHB_CLK 96106#define CAMSS_CSI2RDI_CLK 97107#define CAMSS_CSI2PIX_CLK 98108#define CAMSS_CSI3_CLK 99109#define CAMSS_CSI3_AHB_CLK 100110#define CAMSS_CSI3RDI_CLK 101111#define CAMSS_CSI3PIX_CLK 102112#define CAMSS_ISPIF_AHB_CLK 103113#define CAMSS_CCI_CLK 104114#define CAMSS_CCI_AHB_CLK 105115#define CAMSS_MCLK0_CLK 106116#define CAMSS_MCLK1_CLK 107117#define CAMSS_MCLK2_CLK 108118#define CAMSS_MCLK3_CLK 109119#define CAMSS_TOP_AHB_CLK 110120#define CAMSS_AHB_CLK 111121#define CAMSS_MICRO_AHB_CLK 112122#define CAMSS_JPEG0_CLK 113123#define CAMSS_JPEG_AHB_CLK 114124#define CAMSS_JPEG_AXI_CLK 115125#define CAMSS_VFE0_AHB_CLK 116126#define CAMSS_VFE1_AHB_CLK 117127#define CAMSS_VFE0_CLK 118128#define CAMSS_VFE1_CLK 119129#define CAMSS_CPP_CLK 120130#define CAMSS_CPP_AHB_CLK 121131#define CAMSS_VFE_VBIF_AHB_CLK 122132#define CAMSS_VFE_VBIF_AXI_CLK 123133#define CAMSS_CPP_AXI_CLK 124134#define CAMSS_CPP_VBIF_AHB_CLK 125135#define CAMSS_CSI_VFE0_CLK 126136#define CAMSS_CSI_VFE1_CLK 127137#define CAMSS_VFE0_STREAM_CLK 128138#define CAMSS_VFE1_STREAM_CLK 129139#define CAMSS_CPHY_CSID0_CLK 130140#define CAMSS_CPHY_CSID1_CLK 131141#define CAMSS_CPHY_CSID2_CLK 132142#define CAMSS_CPHY_CSID3_CLK 133143#define CAMSS_CSIPHY0_CLK 134144#define CAMSS_CSIPHY1_CLK 135145#define CAMSS_CSIPHY2_CLK 136146#define FD_CORE_CLK 137147#define FD_CORE_UAR_CLK 138148#define FD_AHB_CLK 139149#define MNOC_AHB_CLK 140150#define BIMC_SMMU_AHB_CLK 141151#define BIMC_SMMU_AXI_CLK 142152#define MNOC_MAXI_CLK 143153#define VMEM_MAXI_CLK 144154#define VMEM_AHB_CLK 145155 156#define SPDM_BCR 0157#define SPDM_RM_BCR 1158#define MISC_BCR 2159#define VIDEO_TOP_BCR 3160#define THROTTLE_VIDEO_BCR 4161#define MDSS_BCR 5162#define THROTTLE_MDSS_BCR 6163#define CAMSS_PHY0_BCR 7164#define CAMSS_PHY1_BCR 8165#define CAMSS_PHY2_BCR 9166#define CAMSS_CSI0_BCR 10167#define CAMSS_CSI0RDI_BCR 11168#define CAMSS_CSI0PIX_BCR 12169#define CAMSS_CSI1_BCR 13170#define CAMSS_CSI1RDI_BCR 14171#define CAMSS_CSI1PIX_BCR 15172#define CAMSS_CSI2_BCR 16173#define CAMSS_CSI2RDI_BCR 17174#define CAMSS_CSI2PIX_BCR 18175#define CAMSS_CSI3_BCR 19176#define CAMSS_CSI3RDI_BCR 20177#define CAMSS_CSI3PIX_BCR 21178#define CAMSS_ISPIF_BCR 22179#define CAMSS_CCI_BCR 23180#define CAMSS_TOP_BCR 24181#define CAMSS_AHB_BCR 25182#define CAMSS_MICRO_BCR 26183#define CAMSS_JPEG_BCR 27184#define CAMSS_VFE0_BCR 28185#define CAMSS_VFE1_BCR 29186#define CAMSS_VFE_VBIF_BCR 30187#define CAMSS_CPP_TOP_BCR 31188#define CAMSS_CPP_BCR 32189#define CAMSS_CSI_VFE0_BCR 33190#define CAMSS_CSI_VFE1_BCR 34191#define CAMSS_FD_BCR 35192#define THROTTLE_CAMSS_BCR 36193#define MNOCAHB_BCR 37194#define MNOCAXI_BCR 38195#define BMIC_SMMU_BCR 39196#define MNOC_MAXI_BCR 40197#define VMEM_BCR 41198#define BTO_BCR 42199 200#define VIDEO_TOP_GDSC 1201#define VIDEO_SUBCORE0_GDSC 2202#define VIDEO_SUBCORE1_GDSC 3203#define MDSS_GDSC 4204#define CAMSS_TOP_GDSC 5205#define CAMSS_VFE0_GDSC 6206#define CAMSS_VFE1_GDSC 7207#define CAMSS_CPP_GDSC 8208#define BIMC_SMMU_GDSC 9209 210#endif211