178 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */2/*3 * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.4 */5 6#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H7#define _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H8 9/* GCC clocks */10#define GCC_GPLL0 011#define GCC_GPLL0_OUT_EVEN 112#define GCC_GPLL1 213#define GCC_GPLL2 314#define GCC_GPLL2_OUT_EVEN 415#define GCC_GPLL3 516#define GCC_GPLL4 617#define GCC_GPLL5 718#define GCC_GPLL5_OUT_EVEN 819#define GCC_GPLL6 920#define GCC_GPLL7 1021#define GCC_GPLL8 1122#define GCC_AGGRE_NOC_ECPRI_DMA_CLK 1223#define GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC 1324#define GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC 1425#define GCC_BOOT_ROM_AHB_CLK 1526#define GCC_CFG_NOC_ECPRI_CC_AHB_CLK 1627#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 1728#define GCC_DDRSS_ECPRI_DMA_CLK 1829#define GCC_ECPRI_AHB_CLK 1930#define GCC_ECPRI_CC_GPLL0_CLK_SRC 2031#define GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC 2132#define GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC 2233#define GCC_ECPRI_CC_GPLL3_CLK_SRC 2334#define GCC_ECPRI_CC_GPLL4_CLK_SRC 2435#define GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC 2536#define GCC_ECPRI_XO_CLK 2637#define GCC_ETH_DBG_SNOC_AXI_CLK 2738#define GCC_GEMNOC_PCIE_QX_CLK 2839#define GCC_GP1_CLK 2940#define GCC_GP1_CLK_SRC 3041#define GCC_GP2_CLK 3142#define GCC_GP2_CLK_SRC 3243#define GCC_GP3_CLK 3344#define GCC_GP3_CLK_SRC 3445#define GCC_PCIE_0_AUX_CLK 3546#define GCC_PCIE_0_AUX_CLK_SRC 3647#define GCC_PCIE_0_CFG_AHB_CLK 3748#define GCC_PCIE_0_CLKREF_EN 3849#define GCC_PCIE_0_MSTR_AXI_CLK 3950#define GCC_PCIE_0_PHY_AUX_CLK 4051#define GCC_PCIE_0_PHY_RCHNG_CLK 4152#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 4253#define GCC_PCIE_0_PIPE_CLK 4354#define GCC_PCIE_0_SLV_AXI_CLK 4455#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 4556#define GCC_PDM2_CLK 4657#define GCC_PDM2_CLK_SRC 4758#define GCC_PDM_AHB_CLK 4859#define GCC_PDM_XO4_CLK 4960#define GCC_QMIP_ANOC_PCIE_CLK 5061#define GCC_QMIP_ECPRI_DMA0_CLK 5162#define GCC_QMIP_ECPRI_DMA1_CLK 5263#define GCC_QMIP_ECPRI_GSI_CLK 5364#define GCC_QUPV3_WRAP0_CORE_2X_CLK 5465#define GCC_QUPV3_WRAP0_CORE_CLK 5566#define GCC_QUPV3_WRAP0_S0_CLK 5667#define GCC_QUPV3_WRAP0_S0_CLK_SRC 5768#define GCC_QUPV3_WRAP0_S1_CLK 5869#define GCC_QUPV3_WRAP0_S1_CLK_SRC 5970#define GCC_QUPV3_WRAP0_S2_CLK 6071#define GCC_QUPV3_WRAP0_S2_CLK_SRC 6172#define GCC_QUPV3_WRAP0_S3_CLK 6273#define GCC_QUPV3_WRAP0_S3_CLK_SRC 6374#define GCC_QUPV3_WRAP0_S4_CLK 6475#define GCC_QUPV3_WRAP0_S4_CLK_SRC 6576#define GCC_QUPV3_WRAP0_S5_CLK 6677#define GCC_QUPV3_WRAP0_S5_CLK_SRC 6778#define GCC_QUPV3_WRAP0_S6_CLK 6879#define GCC_QUPV3_WRAP0_S6_CLK_SRC 6980#define GCC_QUPV3_WRAP0_S7_CLK 7081#define GCC_QUPV3_WRAP0_S7_CLK_SRC 7182#define GCC_QUPV3_WRAP1_CORE_2X_CLK 7283#define GCC_QUPV3_WRAP1_CORE_CLK 7384#define GCC_QUPV3_WRAP1_S0_CLK 7485#define GCC_QUPV3_WRAP1_S0_CLK_SRC 7586#define GCC_QUPV3_WRAP1_S1_CLK 7687#define GCC_QUPV3_WRAP1_S1_CLK_SRC 7788#define GCC_QUPV3_WRAP1_S2_CLK 7889#define GCC_QUPV3_WRAP1_S2_CLK_SRC 7990#define GCC_QUPV3_WRAP1_S3_CLK 8091#define GCC_QUPV3_WRAP1_S3_CLK_SRC 8192#define GCC_QUPV3_WRAP1_S4_CLK 8293#define GCC_QUPV3_WRAP1_S4_CLK_SRC 8394#define GCC_QUPV3_WRAP1_S5_CLK 8495#define GCC_QUPV3_WRAP1_S5_CLK_SRC 8596#define GCC_QUPV3_WRAP1_S6_CLK 8697#define GCC_QUPV3_WRAP1_S6_CLK_SRC 8798#define GCC_QUPV3_WRAP1_S7_CLK 8899#define GCC_QUPV3_WRAP1_S7_CLK_SRC 89100#define GCC_QUPV3_WRAP_0_M_AHB_CLK 90101#define GCC_QUPV3_WRAP_0_S_AHB_CLK 91102#define GCC_QUPV3_WRAP_1_M_AHB_CLK 92103#define GCC_QUPV3_WRAP_1_S_AHB_CLK 93104#define GCC_SDCC5_AHB_CLK 94105#define GCC_SDCC5_APPS_CLK 95106#define GCC_SDCC5_APPS_CLK_SRC 96107#define GCC_SDCC5_ICE_CORE_CLK 97108#define GCC_SDCC5_ICE_CORE_CLK_SRC 98109#define GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK 99110#define GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK 100111#define GCC_SNOC_CNOC_PCIE_QX_CLK 101112#define GCC_SNOC_PCIE_SF_CENTER_QX_CLK 102113#define GCC_SNOC_PCIE_SF_SOUTH_QX_CLK 103114#define GCC_TSC_CFG_AHB_CLK 104115#define GCC_TSC_CLK_SRC 105116#define GCC_TSC_CNTR_CLK 106117#define GCC_TSC_ETU_CLK 107118#define GCC_USB2_CLKREF_EN 108119#define GCC_USB30_PRIM_MASTER_CLK 109120#define GCC_USB30_PRIM_MASTER_CLK_SRC 110121#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111122#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112123#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 113124#define GCC_USB30_PRIM_SLEEP_CLK 114125#define GCC_USB3_PRIM_PHY_AUX_CLK 115126#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116127#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117128#define GCC_USB3_PRIM_PHY_PIPE_CLK 118129#define GCC_SM_BUS_AHB_CLK 119130#define GCC_SM_BUS_XO_CLK 120131#define GCC_SM_BUS_XO_CLK_SRC 121132#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 122133#define GCC_ETH_100G_C2C_HM_APB_CLK 123134#define GCC_ETH_100G_FH_HM_APB_0_CLK 124135#define GCC_ETH_100G_FH_HM_APB_1_CLK 125136#define GCC_ETH_100G_FH_HM_APB_2_CLK 126137#define GCC_ETH_DBG_C2C_HM_APB_CLK 127138#define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128139#define GCC_PCIE_0_PIPE_CLK_SRC 129140#define GCC_PCIE_0_PHY_AUX_CLK_SRC 130141#define GCC_GPLL1_OUT_EVEN 131142#define GCC_DDRSS_ECPRI_GSI_CLK 132143 144/* GCC resets */145#define GCC_ECPRI_CC_BCR 0146#define GCC_ECPRI_SS_BCR 1147#define GCC_ETH_WRAPPER_BCR 2148#define GCC_PCIE_0_BCR 3149#define GCC_PCIE_0_LINK_DOWN_BCR 4150#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5151#define GCC_PCIE_0_PHY_BCR 6152#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7153#define GCC_PCIE_PHY_CFG_AHB_BCR 8154#define GCC_PCIE_PHY_COM_BCR 9155#define GCC_PDM_BCR 10156#define GCC_QUPV3_WRAPPER_0_BCR 11157#define GCC_QUPV3_WRAPPER_1_BCR 12158#define GCC_QUSB2PHY_PRIM_BCR 13159#define GCC_QUSB2PHY_SEC_BCR 14160#define GCC_SDCC5_BCR 15161#define GCC_TCSR_PCIE_BCR 16162#define GCC_TSC_BCR 17163#define GCC_USB30_PRIM_BCR 18164#define GCC_USB3_DP_PHY_PRIM_BCR 19165#define GCC_USB3_DP_PHY_SEC_BCR 20166#define GCC_USB3_PHY_PRIM_BCR 21167#define GCC_USB3_PHY_SEC_BCR 22168#define GCC_USB3PHY_PHY_PRIM_BCR 23169#define GCC_USB3PHY_PHY_SEC_BCR 24170#define GCC_USB_PHY_CFG_AHB2PHY_BCR 25171 172/* GCC power domains */173#define PCIE_0_GDSC 0174#define PCIE_0_PHY_GDSC 1175#define USB30_PRIM_GDSC 2176 177#endif178