321 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.4 * Copyright (c) 2023, Linaro Limited5 */6 7#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H8#define _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H9 10/* GCC clocks */11#define GCC_GPLL0 012#define GCC_GPLL0_OUT_EVEN 113#define GCC_GPLL1 214#define GCC_GPLL4 315#define GCC_GPLL5 416#define GCC_GPLL7 517#define GCC_GPLL9 618#define GCC_AGGRE_NOC_QUPV3_AXI_CLK 719#define GCC_AGGRE_UFS_CARD_AXI_CLK 820#define GCC_AGGRE_UFS_PHY_AXI_CLK 921#define GCC_AGGRE_USB2_PRIM_AXI_CLK 1022#define GCC_AGGRE_USB3_PRIM_AXI_CLK 1123#define GCC_AGGRE_USB3_SEC_AXI_CLK 1224#define GCC_AHB2PHY0_CLK 1325#define GCC_AHB2PHY2_CLK 1426#define GCC_AHB2PHY3_CLK 1527#define GCC_BOOT_ROM_AHB_CLK 1628#define GCC_CAMERA_AHB_CLK 1729#define GCC_CAMERA_HF_AXI_CLK 1830#define GCC_CAMERA_SF_AXI_CLK 1931#define GCC_CAMERA_THROTTLE_XO_CLK 2032#define GCC_CAMERA_XO_CLK 2133#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 2234#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 2335#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 2436#define GCC_DDRSS_GPU_AXI_CLK 2537#define GCC_DISP1_AHB_CLK 2638#define GCC_DISP1_HF_AXI_CLK 2739#define GCC_DISP1_XO_CLK 2840#define GCC_DISP_AHB_CLK 2941#define GCC_DISP_HF_AXI_CLK 3042#define GCC_DISP_XO_CLK 3143#define GCC_EDP_REF_CLKREF_EN 3244#define GCC_EMAC0_AXI_CLK 3345#define GCC_EMAC0_PHY_AUX_CLK 3446#define GCC_EMAC0_PHY_AUX_CLK_SRC 3547#define GCC_EMAC0_PTP_CLK 3648#define GCC_EMAC0_PTP_CLK_SRC 3749#define GCC_EMAC0_RGMII_CLK 3850#define GCC_EMAC0_RGMII_CLK_SRC 3951#define GCC_EMAC0_SLV_AHB_CLK 4052#define GCC_EMAC1_AXI_CLK 4153#define GCC_EMAC1_PHY_AUX_CLK 4254#define GCC_EMAC1_PHY_AUX_CLK_SRC 4355#define GCC_EMAC1_PTP_CLK 4456#define GCC_EMAC1_PTP_CLK_SRC 4557#define GCC_EMAC1_RGMII_CLK 4658#define GCC_EMAC1_RGMII_CLK_SRC 4759#define GCC_EMAC1_SLV_AHB_CLK 4860#define GCC_GP1_CLK 4961#define GCC_GP1_CLK_SRC 5062#define GCC_GP2_CLK 5163#define GCC_GP2_CLK_SRC 5264#define GCC_GP3_CLK 5365#define GCC_GP3_CLK_SRC 5466#define GCC_GP4_CLK 5567#define GCC_GP4_CLK_SRC 5668#define GCC_GP5_CLK 5769#define GCC_GP5_CLK_SRC 5870#define GCC_GPU_CFG_AHB_CLK 5971#define GCC_GPU_GPLL0_CLK_SRC 6072#define GCC_GPU_GPLL0_DIV_CLK_SRC 6173#define GCC_GPU_MEMNOC_GFX_CLK 6274#define GCC_GPU_SNOC_DVM_GFX_CLK 6375#define GCC_GPU_TCU_THROTTLE_AHB_CLK 6476#define GCC_GPU_TCU_THROTTLE_CLK 6577#define GCC_PCIE_0_AUX_CLK 6678#define GCC_PCIE_0_AUX_CLK_SRC 6779#define GCC_PCIE_0_CFG_AHB_CLK 6880#define GCC_PCIE_0_MSTR_AXI_CLK 6981#define GCC_PCIE_0_PHY_AUX_CLK 7082#define GCC_PCIE_0_PHY_AUX_CLK_SRC 7183#define GCC_PCIE_0_PHY_RCHNG_CLK 7284#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 7385#define GCC_PCIE_0_PIPE_CLK 7486#define GCC_PCIE_0_PIPE_CLK_SRC 7587#define GCC_PCIE_0_PIPE_DIV_CLK_SRC 7688#define GCC_PCIE_0_PIPEDIV2_CLK 7789#define GCC_PCIE_0_SLV_AXI_CLK 7890#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 7991#define GCC_PCIE_1_AUX_CLK 8092#define GCC_PCIE_1_AUX_CLK_SRC 8193#define GCC_PCIE_1_CFG_AHB_CLK 8294#define GCC_PCIE_1_MSTR_AXI_CLK 8395#define GCC_PCIE_1_PHY_AUX_CLK 8496#define GCC_PCIE_1_PHY_AUX_CLK_SRC 8597#define GCC_PCIE_1_PHY_RCHNG_CLK 8698#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 8799#define GCC_PCIE_1_PIPE_CLK 88100#define GCC_PCIE_1_PIPE_CLK_SRC 89101#define GCC_PCIE_1_PIPE_DIV_CLK_SRC 90102#define GCC_PCIE_1_PIPEDIV2_CLK 91103#define GCC_PCIE_1_SLV_AXI_CLK 92104#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 93105#define GCC_PCIE_CLKREF_EN 94106#define GCC_PCIE_THROTTLE_CFG_CLK 95107#define GCC_PDM2_CLK 96108#define GCC_PDM2_CLK_SRC 97109#define GCC_PDM_AHB_CLK 98110#define GCC_PDM_XO4_CLK 99111#define GCC_QMIP_CAMERA_NRT_AHB_CLK 100112#define GCC_QMIP_CAMERA_RT_AHB_CLK 101113#define GCC_QMIP_DISP1_AHB_CLK 102114#define GCC_QMIP_DISP1_ROT_AHB_CLK 103115#define GCC_QMIP_DISP_AHB_CLK 104116#define GCC_QMIP_DISP_ROT_AHB_CLK 105117#define GCC_QMIP_VIDEO_CVP_AHB_CLK 106118#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 107119#define GCC_QMIP_VIDEO_VCPU_AHB_CLK 108120#define GCC_QUPV3_WRAP0_CORE_2X_CLK 109121#define GCC_QUPV3_WRAP0_CORE_CLK 110122#define GCC_QUPV3_WRAP0_S0_CLK 111123#define GCC_QUPV3_WRAP0_S0_CLK_SRC 112124#define GCC_QUPV3_WRAP0_S1_CLK 113125#define GCC_QUPV3_WRAP0_S1_CLK_SRC 114126#define GCC_QUPV3_WRAP0_S2_CLK 115127#define GCC_QUPV3_WRAP0_S2_CLK_SRC 116128#define GCC_QUPV3_WRAP0_S3_CLK 117129#define GCC_QUPV3_WRAP0_S3_CLK_SRC 118130#define GCC_QUPV3_WRAP0_S4_CLK 119131#define GCC_QUPV3_WRAP0_S4_CLK_SRC 120132#define GCC_QUPV3_WRAP0_S5_CLK 121133#define GCC_QUPV3_WRAP0_S5_CLK_SRC 122134#define GCC_QUPV3_WRAP0_S6_CLK 123135#define GCC_QUPV3_WRAP0_S6_CLK_SRC 124136#define GCC_QUPV3_WRAP1_CORE_2X_CLK 125137#define GCC_QUPV3_WRAP1_CORE_CLK 126138#define GCC_QUPV3_WRAP1_S0_CLK 127139#define GCC_QUPV3_WRAP1_S0_CLK_SRC 128140#define GCC_QUPV3_WRAP1_S1_CLK 129141#define GCC_QUPV3_WRAP1_S1_CLK_SRC 130142#define GCC_QUPV3_WRAP1_S2_CLK 131143#define GCC_QUPV3_WRAP1_S2_CLK_SRC 132144#define GCC_QUPV3_WRAP1_S3_CLK 133145#define GCC_QUPV3_WRAP1_S3_CLK_SRC 134146#define GCC_QUPV3_WRAP1_S4_CLK 135147#define GCC_QUPV3_WRAP1_S4_CLK_SRC 136148#define GCC_QUPV3_WRAP1_S5_CLK 137149#define GCC_QUPV3_WRAP1_S5_CLK_SRC 138150#define GCC_QUPV3_WRAP1_S6_CLK 139151#define GCC_QUPV3_WRAP1_S6_CLK_SRC 140152#define GCC_QUPV3_WRAP2_CORE_2X_CLK 141153#define GCC_QUPV3_WRAP2_CORE_CLK 142154#define GCC_QUPV3_WRAP2_S0_CLK 143155#define GCC_QUPV3_WRAP2_S0_CLK_SRC 144156#define GCC_QUPV3_WRAP2_S1_CLK 145157#define GCC_QUPV3_WRAP2_S1_CLK_SRC 146158#define GCC_QUPV3_WRAP2_S2_CLK 147159#define GCC_QUPV3_WRAP2_S2_CLK_SRC 148160#define GCC_QUPV3_WRAP2_S3_CLK 149161#define GCC_QUPV3_WRAP2_S3_CLK_SRC 150162#define GCC_QUPV3_WRAP2_S4_CLK 151163#define GCC_QUPV3_WRAP2_S4_CLK_SRC 152164#define GCC_QUPV3_WRAP2_S5_CLK 153165#define GCC_QUPV3_WRAP2_S5_CLK_SRC 154166#define GCC_QUPV3_WRAP2_S6_CLK 155167#define GCC_QUPV3_WRAP2_S6_CLK_SRC 156168#define GCC_QUPV3_WRAP3_CORE_2X_CLK 157169#define GCC_QUPV3_WRAP3_CORE_CLK 158170#define GCC_QUPV3_WRAP3_QSPI_CLK 159171#define GCC_QUPV3_WRAP3_S0_CLK 160172#define GCC_QUPV3_WRAP3_S0_CLK_SRC 161173#define GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC 162174#define GCC_QUPV3_WRAP_0_M_AHB_CLK 163175#define GCC_QUPV3_WRAP_0_S_AHB_CLK 164176#define GCC_QUPV3_WRAP_1_M_AHB_CLK 165177#define GCC_QUPV3_WRAP_1_S_AHB_CLK 166178#define GCC_QUPV3_WRAP_2_M_AHB_CLK 167179#define GCC_QUPV3_WRAP_2_S_AHB_CLK 168180#define GCC_QUPV3_WRAP_3_M_AHB_CLK 169181#define GCC_QUPV3_WRAP_3_S_AHB_CLK 170182#define GCC_SDCC1_AHB_CLK 171183#define GCC_SDCC1_APPS_CLK 172184#define GCC_SDCC1_APPS_CLK_SRC 173185#define GCC_SDCC1_ICE_CORE_CLK 174186#define GCC_SDCC1_ICE_CORE_CLK_SRC 175187#define GCC_SGMI_CLKREF_EN 176188#define GCC_TSCSS_AHB_CLK 177189#define GCC_TSCSS_CNTR_CLK_SRC 178190#define GCC_TSCSS_ETU_CLK 179191#define GCC_TSCSS_GLOBAL_CNTR_CLK 180192#define GCC_UFS_CARD_AHB_CLK 181193#define GCC_UFS_CARD_AXI_CLK 182194#define GCC_UFS_CARD_AXI_CLK_SRC 183195#define GCC_UFS_CARD_ICE_CORE_CLK 184196#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 185197#define GCC_UFS_CARD_PHY_AUX_CLK 186198#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 187199#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 188200#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 189201#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 190202#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 191203#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 192204#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 193205#define GCC_UFS_CARD_UNIPRO_CORE_CLK 194206#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 195207#define GCC_UFS_PHY_AHB_CLK 196208#define GCC_UFS_PHY_AXI_CLK 197209#define GCC_UFS_PHY_AXI_CLK_SRC 198210#define GCC_UFS_PHY_ICE_CORE_CLK 199211#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 200212#define GCC_UFS_PHY_PHY_AUX_CLK 201213#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 202214#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 203215#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 204216#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 205217#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 206218#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 207219#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 208220#define GCC_UFS_PHY_UNIPRO_CORE_CLK 209221#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 210222#define GCC_USB20_MASTER_CLK 211223#define GCC_USB20_MASTER_CLK_SRC 212224#define GCC_USB20_MOCK_UTMI_CLK 213225#define GCC_USB20_MOCK_UTMI_CLK_SRC 214226#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 215227#define GCC_USB20_SLEEP_CLK 216228#define GCC_USB30_PRIM_MASTER_CLK 217229#define GCC_USB30_PRIM_MASTER_CLK_SRC 218230#define GCC_USB30_PRIM_MOCK_UTMI_CLK 219231#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 220232#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 221233#define GCC_USB30_PRIM_SLEEP_CLK 222234#define GCC_USB30_SEC_MASTER_CLK 223235#define GCC_USB30_SEC_MASTER_CLK_SRC 224236#define GCC_USB30_SEC_MOCK_UTMI_CLK 225237#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 226238#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 227239#define GCC_USB30_SEC_SLEEP_CLK 228240#define GCC_USB3_PRIM_PHY_AUX_CLK 229241#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 230242#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 231243#define GCC_USB3_PRIM_PHY_PIPE_CLK 232244#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 233245#define GCC_USB3_SEC_PHY_AUX_CLK 234246#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 235247#define GCC_USB3_SEC_PHY_COM_AUX_CLK 236248#define GCC_USB3_SEC_PHY_PIPE_CLK 237249#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 238250#define GCC_USB_CLKREF_EN 239251#define GCC_VIDEO_AHB_CLK 240252#define GCC_VIDEO_AXI0_CLK 241253#define GCC_VIDEO_AXI1_CLK 242254#define GCC_VIDEO_XO_CLK 243255#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 244256#define GCC_UFS_PHY_AXI_HW_CTL_CLK 245257#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 246258#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 247259#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 248260 261/* GCC resets */262#define GCC_CAMERA_BCR 0263#define GCC_DISPLAY1_BCR 1264#define GCC_DISPLAY_BCR 2265#define GCC_EMAC0_BCR 3266#define GCC_EMAC1_BCR 4267#define GCC_GPU_BCR 5268#define GCC_MMSS_BCR 6269#define GCC_PCIE_0_BCR 7270#define GCC_PCIE_0_LINK_DOWN_BCR 8271#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 9272#define GCC_PCIE_0_PHY_BCR 10273#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 11274#define GCC_PCIE_1_BCR 12275#define GCC_PCIE_1_LINK_DOWN_BCR 13276#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 14277#define GCC_PCIE_1_PHY_BCR 15278#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 16279#define GCC_PDM_BCR 17280#define GCC_QUPV3_WRAPPER_0_BCR 18281#define GCC_QUPV3_WRAPPER_1_BCR 19282#define GCC_QUPV3_WRAPPER_2_BCR 20283#define GCC_QUPV3_WRAPPER_3_BCR 21284#define GCC_SDCC1_BCR 22285#define GCC_TSCSS_BCR 23286#define GCC_UFS_CARD_BCR 24287#define GCC_UFS_PHY_BCR 25288#define GCC_USB20_PRIM_BCR 26289#define GCC_USB2_PHY_PRIM_BCR 27290#define GCC_USB2_PHY_SEC_BCR 28291#define GCC_USB30_PRIM_BCR 29292#define GCC_USB30_SEC_BCR 30293#define GCC_USB3_DP_PHY_PRIM_BCR 31294#define GCC_USB3_DP_PHY_SEC_BCR 32295#define GCC_USB3_PHY_PRIM_BCR 33296#define GCC_USB3_PHY_SEC_BCR 34297#define GCC_USB3_PHY_TERT_BCR 35298#define GCC_USB3_UNIPHY_MP0_BCR 36299#define GCC_USB3_UNIPHY_MP1_BCR 37300#define GCC_USB3PHY_PHY_PRIM_BCR 38301#define GCC_USB3PHY_PHY_SEC_BCR 39302#define GCC_USB3UNIPHY_PHY_MP0_BCR 40303#define GCC_USB3UNIPHY_PHY_MP1_BCR 41304#define GCC_USB_PHY_CFG_AHB2PHY_BCR 42305#define GCC_VIDEO_BCR 43306#define GCC_VIDEO_AXI0_CLK_ARES 44307#define GCC_VIDEO_AXI1_CLK_ARES 45308 309/* GCC GDSCs */310#define PCIE_0_GDSC 0311#define PCIE_1_GDSC 1312#define UFS_CARD_GDSC 2313#define UFS_PHY_GDSC 3314#define USB20_PRIM_GDSC 4315#define USB30_PRIM_GDSC 5316#define USB30_SEC_GDSC 6317#define EMAC0_GDSC 7318#define EMAC1_GDSC 8319 320#endif /* _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H */321