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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.4 */5 6#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H7#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H8 9/* DISP_CC clocks */10#define DISP_CC_MDSS_AHB1_CLK 011#define DISP_CC_MDSS_AHB_CLK 112#define DISP_CC_MDSS_AHB_CLK_SRC 213#define DISP_CC_MDSS_BYTE0_CLK 314#define DISP_CC_MDSS_BYTE0_CLK_SRC 415#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 516#define DISP_CC_MDSS_BYTE0_INTF_CLK 617#define DISP_CC_MDSS_ESC0_CLK 718#define DISP_CC_MDSS_ESC0_CLK_SRC 819#define DISP_CC_MDSS_MDP1_CLK 920#define DISP_CC_MDSS_MDP_CLK 1021#define DISP_CC_MDSS_MDP_CLK_SRC 1122#define DISP_CC_MDSS_MDP_LUT1_CLK 1223#define DISP_CC_MDSS_MDP_LUT_CLK 1324#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 1425#define DISP_CC_MDSS_PCLK0_CLK 1526#define DISP_CC_MDSS_PCLK0_CLK_SRC 1627#define DISP_CC_MDSS_ROT1_CLK 1728#define DISP_CC_MDSS_ROT_CLK 1829#define DISP_CC_MDSS_ROT_CLK_SRC 1930#define DISP_CC_MDSS_RSCC_AHB_CLK 2031#define DISP_CC_MDSS_RSCC_VSYNC_CLK 2132#define DISP_CC_MDSS_VSYNC1_CLK 2233#define DISP_CC_MDSS_VSYNC_CLK 2334#define DISP_CC_MDSS_VSYNC_CLK_SRC 2435#define DISP_CC_PLL0 2536#define DISP_CC_PLL1 2637#define DISP_CC_SLEEP_CLK 2738#define DISP_CC_SLEEP_CLK_SRC 2839#define DISP_CC_XO_CLK 2940#define DISP_CC_XO_CLK_SRC 3041 42/* DISP_CC power domains */43#define DISP_CC_MDSS_CORE_GDSC 044#define DISP_CC_MDSS_CORE_INT2_GDSC 145 46/* DISP_CC resets */47#define DISP_CC_MDSS_CORE_BCR 048#define DISP_CC_MDSS_CORE_INT2_BCR 149#define DISP_CC_MDSS_RSCC_BCR 250 51#endif52