198 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.4 */5 6#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM4450_H7#define _DT_BINDINGS_CLK_QCOM_GCC_SM4450_H8 9/* GCC clocks */10#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 011#define GCC_AGGRE_UFS_PHY_AXI_CLK 112#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 213#define GCC_AGGRE_USB3_PRIM_AXI_CLK 314#define GCC_BOOT_ROM_AHB_CLK 415#define GCC_CAMERA_AHB_CLK 516#define GCC_CAMERA_HF_AXI_CLK 617#define GCC_CAMERA_SF_AXI_CLK 718#define GCC_CAMERA_SLEEP_CLK 819#define GCC_CAMERA_XO_CLK 920#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 1021#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 1122#define GCC_DDRSS_GPU_AXI_CLK 1223#define GCC_DDRSS_PCIE_SF_TBU_CLK 1324#define GCC_DISP_AHB_CLK 1425#define GCC_DISP_HF_AXI_CLK 1526#define GCC_DISP_XO_CLK 1627#define GCC_EUSB3_0_CLKREF_EN 1728#define GCC_GP1_CLK 1829#define GCC_GP1_CLK_SRC 1930#define GCC_GP2_CLK 2031#define GCC_GP2_CLK_SRC 2132#define GCC_GP3_CLK 2233#define GCC_GP3_CLK_SRC 2334#define GCC_GPLL0 2435#define GCC_GPLL0_OUT_EVEN 2536#define GCC_GPLL0_OUT_ODD 2637#define GCC_GPLL1 2738#define GCC_GPLL3 2839#define GCC_GPLL4 2940#define GCC_GPLL9 3041#define GCC_GPLL10 3142#define GCC_GPU_CFG_AHB_CLK 3243#define GCC_GPU_GPLL0_CLK_SRC 3344#define GCC_GPU_GPLL0_DIV_CLK_SRC 3445#define GCC_GPU_MEMNOC_GFX_CLK 3546#define GCC_GPU_SNOC_DVM_GFX_CLK 3647#define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK 3748#define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK 3849#define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK 3950#define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK 4051#define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK 4152#define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK 4253#define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK 4354#define GCC_HLOS1_VOTE_MMU_TCU_CLK 4455#define GCC_PCIE_0_AUX_CLK 4556#define GCC_PCIE_0_AUX_CLK_SRC 4657#define GCC_PCIE_0_CFG_AHB_CLK 4758#define GCC_PCIE_0_CLKREF_EN 4859#define GCC_PCIE_0_MSTR_AXI_CLK 4960#define GCC_PCIE_0_PHY_RCHNG_CLK 5061#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 5162#define GCC_PCIE_0_PIPE_CLK 5263#define GCC_PCIE_0_PIPE_CLK_SRC 5364#define GCC_PCIE_0_PIPE_DIV2_CLK 5465#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC 5566#define GCC_PCIE_0_SLV_AXI_CLK 5667#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 5768#define GCC_PDM2_CLK 5869#define GCC_PDM2_CLK_SRC 5970#define GCC_PDM_AHB_CLK 6071#define GCC_PDM_XO4_CLK 6172#define GCC_QMIP_CAMERA_NRT_AHB_CLK 6273#define GCC_QMIP_CAMERA_RT_AHB_CLK 6374#define GCC_QMIP_DISP_AHB_CLK 6475#define GCC_QMIP_GPU_AHB_CLK 6576#define GCC_QMIP_PCIE_AHB_CLK 6677#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 6778#define GCC_QUPV3_WRAP0_CORE_2X_CLK 6879#define GCC_QUPV3_WRAP0_CORE_CLK 6980#define GCC_QUPV3_WRAP0_S0_CLK 7081#define GCC_QUPV3_WRAP0_S0_CLK_SRC 7182#define GCC_QUPV3_WRAP0_S1_CLK 7283#define GCC_QUPV3_WRAP0_S1_CLK_SRC 7384#define GCC_QUPV3_WRAP0_S2_CLK 7485#define GCC_QUPV3_WRAP0_S2_CLK_SRC 7586#define GCC_QUPV3_WRAP0_S3_CLK 7687#define GCC_QUPV3_WRAP0_S3_CLK_SRC 7788#define GCC_QUPV3_WRAP0_S4_CLK 7889#define GCC_QUPV3_WRAP0_S4_CLK_SRC 7990#define GCC_QUPV3_WRAP1_CORE_2X_CLK 8091#define GCC_QUPV3_WRAP1_CORE_CLK 8192#define GCC_QUPV3_WRAP1_S0_CLK 8293#define GCC_QUPV3_WRAP1_S0_CLK_SRC 8394#define GCC_QUPV3_WRAP1_S1_CLK 8495#define GCC_QUPV3_WRAP1_S1_CLK_SRC 8596#define GCC_QUPV3_WRAP1_S2_CLK 8697#define GCC_QUPV3_WRAP1_S2_CLK_SRC 8798#define GCC_QUPV3_WRAP1_S3_CLK 8899#define GCC_QUPV3_WRAP1_S3_CLK_SRC 89100#define GCC_QUPV3_WRAP1_S4_CLK 90101#define GCC_QUPV3_WRAP1_S4_CLK_SRC 91102#define GCC_QUPV3_WRAP_0_M_AHB_CLK 92103#define GCC_QUPV3_WRAP_0_S_AHB_CLK 93104#define GCC_QUPV3_WRAP_1_M_AHB_CLK 94105#define GCC_QUPV3_WRAP_1_S_AHB_CLK 95106#define GCC_SDCC1_AHB_CLK 96107#define GCC_SDCC1_APPS_CLK 97108#define GCC_SDCC1_APPS_CLK_SRC 98109#define GCC_SDCC1_ICE_CORE_CLK 99110#define GCC_SDCC1_ICE_CORE_CLK_SRC 100111#define GCC_SDCC2_AHB_CLK 101112#define GCC_SDCC2_APPS_CLK 102113#define GCC_SDCC2_APPS_CLK_SRC 103114#define GCC_UFS_0_CLKREF_EN 104115#define GCC_UFS_PAD_CLKREF_EN 105116#define GCC_UFS_PHY_AHB_CLK 106117#define GCC_UFS_PHY_AXI_CLK 107118#define GCC_UFS_PHY_AXI_CLK_SRC 108119#define GCC_UFS_PHY_AXI_HW_CTL_CLK 109120#define GCC_UFS_PHY_ICE_CORE_CLK 110121#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 111122#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 112123#define GCC_UFS_PHY_PHY_AUX_CLK 113124#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 114125#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 115126#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 116127#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 117128#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 118129#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 119130#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 120131#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 121132#define GCC_UFS_PHY_UNIPRO_CORE_CLK 122133#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 123134#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 124135#define GCC_USB30_PRIM_MASTER_CLK 125136#define GCC_USB30_PRIM_MASTER_CLK_SRC 126137#define GCC_USB30_PRIM_MOCK_UTMI_CLK 127138#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 128139#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 129140#define GCC_USB30_PRIM_SLEEP_CLK 130141#define GCC_USB3_0_CLKREF_EN 131142#define GCC_USB3_PRIM_PHY_AUX_CLK 132143#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 133144#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 134145#define GCC_USB3_PRIM_PHY_PIPE_CLK 135146#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 136147#define GCC_VCODEC0_AXI_CLK 137148#define GCC_VENUS_CTL_AXI_CLK 138149#define GCC_VIDEO_AHB_CLK 139150#define GCC_VIDEO_THROTTLE_CORE_CLK 140151#define GCC_VIDEO_VCODEC0_SYS_CLK 141152#define GCC_VIDEO_VENUS_CLK_SRC 142153#define GCC_VIDEO_VENUS_CTL_CLK 143154#define GCC_VIDEO_XO_CLK 144155 156/* GCC power domains */157#define GCC_PCIE_0_GDSC 0158#define GCC_UFS_PHY_GDSC 1159#define GCC_USB30_PRIM_GDSC 2160#define GCC_VCODEC0_GDSC 3161#define GCC_VENUS_GDSC 4162 163/* GCC resets */164#define GCC_CAMERA_BCR 0165#define GCC_DISPLAY_BCR 1166#define GCC_GPU_BCR 2167#define GCC_PCIE_0_BCR 3168#define GCC_PCIE_0_LINK_DOWN_BCR 4169#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5170#define GCC_PCIE_0_PHY_BCR 6171#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7172#define GCC_PCIE_PHY_BCR 8173#define GCC_PCIE_PHY_CFG_AHB_BCR 9174#define GCC_PCIE_PHY_COM_BCR 10175#define GCC_PDM_BCR 11176#define GCC_QUPV3_WRAPPER_0_BCR 12177#define GCC_QUPV3_WRAPPER_1_BCR 13178#define GCC_QUSB2PHY_PRIM_BCR 14179#define GCC_QUSB2PHY_SEC_BCR 15180#define GCC_SDCC1_BCR 16181#define GCC_SDCC2_BCR 17182#define GCC_UFS_PHY_BCR 18183#define GCC_USB30_PRIM_BCR 19184#define GCC_USB3_DP_PHY_PRIM_BCR 20185#define GCC_USB3_DP_PHY_SEC_BCR 21186#define GCC_USB3_PHY_PRIM_BCR 22187#define GCC_USB3_PHY_SEC_BCR 23188#define GCC_USB3PHY_PHY_PRIM_BCR 24189#define GCC_USB3PHY_PHY_SEC_BCR 25190#define GCC_VCODEC0_BCR 26191#define GCC_VENUS_BCR 27192#define GCC_VIDEO_BCR 28193#define GCC_VIDEO_VENUS_BCR 29194#define GCC_VENUS_CTL_AXI_CLK_ARES 30195#define GCC_VIDEO_VENUS_CTL_CLK_ARES 31196 197#endif198