235 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.4 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>5 */6 7#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6375_H8#define _DT_BINDINGS_CLK_QCOM_GCC_SM6375_H9 10/* Clocks */11#define GPLL0 012#define GPLL0_OUT_EVEN 113#define GPLL0_OUT_ODD 214#define GPLL1 315#define GPLL10 416#define GPLL11 517#define GPLL3 618#define GPLL3_OUT_EVEN 719#define GPLL4 820#define GPLL5 921#define GPLL6 1022#define GPLL6_OUT_EVEN 1123#define GPLL7 1224#define GPLL8 1325#define GPLL8_OUT_EVEN 1426#define GPLL9 1527#define GPLL9_OUT_MAIN 1628#define GCC_AHB2PHY_CSI_CLK 1729#define GCC_AHB2PHY_USB_CLK 1830#define GCC_BIMC_GPU_AXI_CLK 1931#define GCC_BOOT_ROM_AHB_CLK 2032#define GCC_CAM_THROTTLE_NRT_CLK 2133#define GCC_CAM_THROTTLE_RT_CLK 2234#define GCC_CAMERA_AHB_CLK 2335#define GCC_CAMERA_XO_CLK 2436#define GCC_CAMSS_AXI_CLK 2537#define GCC_CAMSS_AXI_CLK_SRC 2638#define GCC_CAMSS_CAMNOC_ATB_CLK 2739#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 2840#define GCC_CAMSS_CCI_0_CLK 2941#define GCC_CAMSS_CCI_0_CLK_SRC 3042#define GCC_CAMSS_CCI_1_CLK 3143#define GCC_CAMSS_CCI_1_CLK_SRC 3244#define GCC_CAMSS_CPHY_0_CLK 3345#define GCC_CAMSS_CPHY_1_CLK 3446#define GCC_CAMSS_CPHY_2_CLK 3547#define GCC_CAMSS_CPHY_3_CLK 3648#define GCC_CAMSS_CSI0PHYTIMER_CLK 3749#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 3850#define GCC_CAMSS_CSI1PHYTIMER_CLK 3951#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 4052#define GCC_CAMSS_CSI2PHYTIMER_CLK 4153#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 4254#define GCC_CAMSS_CSI3PHYTIMER_CLK 4355#define GCC_CAMSS_CSI3PHYTIMER_CLK_SRC 4456#define GCC_CAMSS_MCLK0_CLK 4557#define GCC_CAMSS_MCLK0_CLK_SRC 4658#define GCC_CAMSS_MCLK1_CLK 4759#define GCC_CAMSS_MCLK1_CLK_SRC 4860#define GCC_CAMSS_MCLK2_CLK 4961#define GCC_CAMSS_MCLK2_CLK_SRC 5062#define GCC_CAMSS_MCLK3_CLK 5163#define GCC_CAMSS_MCLK3_CLK_SRC 5264#define GCC_CAMSS_MCLK4_CLK 5365#define GCC_CAMSS_MCLK4_CLK_SRC 5466#define GCC_CAMSS_NRT_AXI_CLK 5567#define GCC_CAMSS_OPE_AHB_CLK 5668#define GCC_CAMSS_OPE_AHB_CLK_SRC 5769#define GCC_CAMSS_OPE_CLK 5870#define GCC_CAMSS_OPE_CLK_SRC 5971#define GCC_CAMSS_RT_AXI_CLK 6072#define GCC_CAMSS_TFE_0_CLK 6173#define GCC_CAMSS_TFE_0_CLK_SRC 6274#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 6375#define GCC_CAMSS_TFE_0_CSID_CLK 6476#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 6577#define GCC_CAMSS_TFE_1_CLK 6678#define GCC_CAMSS_TFE_1_CLK_SRC 6779#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 6880#define GCC_CAMSS_TFE_1_CSID_CLK 6981#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 7082#define GCC_CAMSS_TFE_2_CLK 7183#define GCC_CAMSS_TFE_2_CLK_SRC 7284#define GCC_CAMSS_TFE_2_CPHY_RX_CLK 7385#define GCC_CAMSS_TFE_2_CSID_CLK 7486#define GCC_CAMSS_TFE_2_CSID_CLK_SRC 7587#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 7688#define GCC_CAMSS_TOP_AHB_CLK 7789#define GCC_CAMSS_TOP_AHB_CLK_SRC 7890#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 7991#define GCC_CPUSS_AHB_CLK_SRC 8092#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 8193#define GCC_CPUSS_GNOC_CLK 8294#define GCC_DISP_AHB_CLK 8395#define GCC_DISP_GPLL0_CLK_SRC 8496#define GCC_DISP_GPLL0_DIV_CLK_SRC 8597#define GCC_DISP_HF_AXI_CLK 8698#define GCC_DISP_SLEEP_CLK 8799#define GCC_DISP_THROTTLE_CORE_CLK 88100#define GCC_DISP_XO_CLK 89101#define GCC_GP1_CLK 90102#define GCC_GP1_CLK_SRC 91103#define GCC_GP2_CLK 92104#define GCC_GP2_CLK_SRC 93105#define GCC_GP3_CLK 94106#define GCC_GP3_CLK_SRC 95107#define GCC_GPU_CFG_AHB_CLK 96108#define GCC_GPU_GPLL0_CLK_SRC 97109#define GCC_GPU_GPLL0_DIV_CLK_SRC 98110#define GCC_GPU_MEMNOC_GFX_CLK 99111#define GCC_GPU_SNOC_DVM_GFX_CLK 100112#define GCC_GPU_THROTTLE_CORE_CLK 101113#define GCC_PDM2_CLK 102114#define GCC_PDM2_CLK_SRC 103115#define GCC_PDM_AHB_CLK 104116#define GCC_PDM_XO4_CLK 105117#define GCC_PRNG_AHB_CLK 106118#define GCC_QMIP_CAMERA_NRT_AHB_CLK 107119#define GCC_QMIP_CAMERA_RT_AHB_CLK 108120#define GCC_QMIP_DISP_AHB_CLK 109121#define GCC_QMIP_GPU_CFG_AHB_CLK 110122#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 111123#define GCC_QUPV3_WRAP0_CORE_2X_CLK 112124#define GCC_QUPV3_WRAP0_CORE_CLK 113125#define GCC_QUPV3_WRAP0_S0_CLK 114126#define GCC_QUPV3_WRAP0_S0_CLK_SRC 115127#define GCC_QUPV3_WRAP0_S1_CLK 116128#define GCC_QUPV3_WRAP0_S1_CLK_SRC 117129#define GCC_QUPV3_WRAP0_S2_CLK 118130#define GCC_QUPV3_WRAP0_S2_CLK_SRC 119131#define GCC_QUPV3_WRAP0_S3_CLK 120132#define GCC_QUPV3_WRAP0_S3_CLK_SRC 121133#define GCC_QUPV3_WRAP0_S4_CLK 122134#define GCC_QUPV3_WRAP0_S4_CLK_SRC 123135#define GCC_QUPV3_WRAP0_S5_CLK 124136#define GCC_QUPV3_WRAP0_S5_CLK_SRC 125137#define GCC_QUPV3_WRAP1_CORE_2X_CLK 126138#define GCC_QUPV3_WRAP1_CORE_CLK 127139#define GCC_QUPV3_WRAP1_S0_CLK 128140#define GCC_QUPV3_WRAP1_S0_CLK_SRC 129141#define GCC_QUPV3_WRAP1_S1_CLK 130142#define GCC_QUPV3_WRAP1_S1_CLK_SRC 131143#define GCC_QUPV3_WRAP1_S2_CLK 132144#define GCC_QUPV3_WRAP1_S2_CLK_SRC 133145#define GCC_QUPV3_WRAP1_S3_CLK 134146#define GCC_QUPV3_WRAP1_S3_CLK_SRC 135147#define GCC_QUPV3_WRAP1_S4_CLK 136148#define GCC_QUPV3_WRAP1_S4_CLK_SRC 137149#define GCC_QUPV3_WRAP1_S5_CLK 138150#define GCC_QUPV3_WRAP1_S5_CLK_SRC 139151#define GCC_QUPV3_WRAP_0_M_AHB_CLK 140152#define GCC_QUPV3_WRAP_0_S_AHB_CLK 141153#define GCC_QUPV3_WRAP_1_M_AHB_CLK 142154#define GCC_QUPV3_WRAP_1_S_AHB_CLK 143155#define GCC_RX5_PCIE_CLKREF_EN_CLK 144156#define GCC_SDCC1_AHB_CLK 145157#define GCC_SDCC1_APPS_CLK 146158#define GCC_SDCC1_APPS_CLK_SRC 147159#define GCC_SDCC1_ICE_CORE_CLK 148160#define GCC_SDCC1_ICE_CORE_CLK_SRC 149161#define GCC_SDCC2_AHB_CLK 150162#define GCC_SDCC2_APPS_CLK 151163#define GCC_SDCC2_APPS_CLK_SRC 152164#define GCC_SYS_NOC_CPUSS_AHB_CLK 153165#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 154166#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 155167#define GCC_UFS_MEM_CLKREF_CLK 156168#define GCC_UFS_PHY_AHB_CLK 157169#define GCC_UFS_PHY_AXI_CLK 158170#define GCC_UFS_PHY_AXI_CLK_SRC 159171#define GCC_UFS_PHY_ICE_CORE_CLK 160172#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 161173#define GCC_UFS_PHY_PHY_AUX_CLK 162174#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 163175#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 164176#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 165177#define GCC_UFS_PHY_UNIPRO_CORE_CLK 166178#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 167179#define GCC_USB30_PRIM_MASTER_CLK 168180#define GCC_USB30_PRIM_MASTER_CLK_SRC 169181#define GCC_USB30_PRIM_MOCK_UTMI_CLK 170182#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 171183#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 172184#define GCC_USB30_PRIM_SLEEP_CLK 173185#define GCC_USB3_PRIM_CLKREF_CLK 174186#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 175187#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 176188#define GCC_USB3_PRIM_PHY_PIPE_CLK 177189#define GCC_VCODEC0_AXI_CLK 178190#define GCC_VENUS_AHB_CLK 179191#define GCC_VENUS_CTL_AXI_CLK 180192#define GCC_VIDEO_AHB_CLK 181193#define GCC_VIDEO_AXI0_CLK 182194#define GCC_VIDEO_THROTTLE_CORE_CLK 183195#define GCC_VIDEO_VCODEC0_SYS_CLK 184196#define GCC_VIDEO_VENUS_CLK_SRC 185197#define GCC_VIDEO_VENUS_CTL_CLK 186198#define GCC_VIDEO_XO_CLK 187199 200/* Resets */201#define GCC_CAMSS_OPE_BCR 0202#define GCC_CAMSS_TFE_BCR 1203#define GCC_CAMSS_TOP_BCR 2204#define GCC_GPU_BCR 3205#define GCC_MMSS_BCR 4206#define GCC_PDM_BCR 5207#define GCC_PRNG_BCR 6208#define GCC_QUPV3_WRAPPER_0_BCR 7209#define GCC_QUPV3_WRAPPER_1_BCR 8210#define GCC_QUSB2PHY_PRIM_BCR 9211#define GCC_QUSB2PHY_SEC_BCR 10212#define GCC_SDCC1_BCR 11213#define GCC_SDCC2_BCR 12214#define GCC_UFS_PHY_BCR 13215#define GCC_USB30_PRIM_BCR 14216#define GCC_USB_PHY_CFG_AHB2PHY_BCR 15217#define GCC_VCODEC0_BCR 16218#define GCC_VENUS_BCR 17219#define GCC_VIDEO_INTERFACE_BCR 18220#define GCC_USB3_DP_PHY_PRIM_BCR 19221#define GCC_USB3_PHY_PRIM_SP0_BCR 20222 223/* GDSCs */224#define USB30_PRIM_GDSC 0225#define UFS_PHY_GDSC 1226#define CAMSS_TOP_GDSC 2227#define VENUS_GDSC 3228#define VCODEC0_GDSC 4229#define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC 5230#define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC 6231#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 7232#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 8233 234#endif235