60 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.4 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>5 * Copyright (c) 2024, David Wronek <david@mainlining.org>6 */7 8#ifndef _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H9#define _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H10 11/* DISPCC clock registers */12#define DISPCC_PLL0 013#define DISPCC_MDSS_AHB_CLK 114#define DISPCC_MDSS_AHB_CLK_SRC 215#define DISPCC_MDSS_BYTE0_CLK 316#define DISPCC_MDSS_BYTE0_CLK_SRC 417#define DISPCC_MDSS_BYTE0_DIV_CLK_SRC 518#define DISPCC_MDSS_BYTE0_INTF_CLK 619#define DISPCC_MDSS_BYTE1_CLK 720#define DISPCC_MDSS_BYTE1_CLK_SRC 821#define DISPCC_MDSS_BYTE1_DIV_CLK_SRC 922#define DISPCC_MDSS_BYTE1_INTF_CLK 1023#define DISPCC_MDSS_DP_AUX_CLK 1124#define DISPCC_MDSS_DP_AUX_CLK_SRC 1225#define DISPCC_MDSS_DP_CRYPTO_CLK 1326#define DISPCC_MDSS_DP_CRYPTO_CLK_SRC 1427#define DISPCC_MDSS_DP_LINK_CLK 1528#define DISPCC_MDSS_DP_LINK_CLK_SRC 1629#define DISPCC_MDSS_DP_LINK_INTF_CLK 1730#define DISPCC_MDSS_DP_PIXEL1_CLK 1831#define DISPCC_MDSS_DP_PIXEL1_CLK_SRC 1932#define DISPCC_MDSS_DP_PIXEL_CLK 2033#define DISPCC_MDSS_DP_PIXEL_CLK_SRC 2134#define DISPCC_MDSS_ESC0_CLK 2235#define DISPCC_MDSS_ESC0_CLK_SRC 2336#define DISPCC_MDSS_ESC1_CLK 2437#define DISPCC_MDSS_ESC1_CLK_SRC 2538#define DISPCC_MDSS_MDP_CLK 2639#define DISPCC_MDSS_MDP_CLK_SRC 2740#define DISPCC_MDSS_MDP_LUT_CLK 2841#define DISPCC_MDSS_NON_GDSC_AHB_CLK 2942#define DISPCC_MDSS_PCLK0_CLK 3043#define DISPCC_MDSS_PCLK0_CLK_SRC 3144#define DISPCC_MDSS_PCLK1_CLK 3245#define DISPCC_MDSS_PCLK1_CLK_SRC 3346#define DISPCC_MDSS_ROT_CLK 3447#define DISPCC_MDSS_ROT_CLK_SRC 3548#define DISPCC_MDSS_RSCC_AHB_CLK 3649#define DISPCC_MDSS_RSCC_VSYNC_CLK 3750#define DISPCC_MDSS_VSYNC_CLK 3851#define DISPCC_MDSS_VSYNC_CLK_SRC 3952#define DISPCC_XO_CLK_SRC 4053#define DISPCC_SLEEP_CLK 4154#define DISPCC_SLEEP_CLK_SRC 4255 56/* DISPCC GDSCR */57#define MDSS_GDSC 058 59#endif60