187 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.4 * Copyright (c) 2023, Danila Tikhonov <danila@jiaxyga.com>5 * Copyright (c) 2023, David Wronek <davidwronek@gmail.com>6 */7 8#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM7150_H9#define _DT_BINDINGS_CLK_QCOM_GCC_SM7150_H10 11/* GCC clock registers */12#define GCC_GPLL0_MAIN_DIV_CDIV 013#define GPLL0 114#define GPLL0_OUT_EVEN 215#define GPLL6 316#define GPLL7 417#define GCC_AGGRE_NOC_PCIE_TBU_CLK 518#define GCC_AGGRE_UFS_PHY_AXI_CLK 619#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 720#define GCC_AGGRE_USB3_PRIM_AXI_CLK 821#define GCC_APC_VS_CLK 922#define GCC_BOOT_ROM_AHB_CLK 1023#define GCC_CAMERA_HF_AXI_CLK 1124#define GCC_CAMERA_SF_AXI_CLK 1225#define GCC_CE1_AHB_CLK 1326#define GCC_CE1_AXI_CLK 1427#define GCC_CE1_CLK 1528#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 1629#define GCC_CPUSS_AHB_CLK 1730#define GCC_CPUSS_AHB_CLK_SRC 1831#define GCC_CPUSS_RBCPR_CLK 1932#define GCC_CPUSS_RBCPR_CLK_SRC 2033#define GCC_DDRSS_GPU_AXI_CLK 2134#define GCC_DISP_GPLL0_CLK_SRC 2235#define GCC_DISP_GPLL0_DIV_CLK_SRC 2336#define GCC_DISP_HF_AXI_CLK 2437#define GCC_DISP_SF_AXI_CLK 2538#define GCC_GP1_CLK 2639#define GCC_GP1_CLK_SRC 2740#define GCC_GP2_CLK 2841#define GCC_GP2_CLK_SRC 2942#define GCC_GP3_CLK 3043#define GCC_GP3_CLK_SRC 3144#define GCC_GPU_GPLL0_CLK_SRC 3245#define GCC_GPU_GPLL0_DIV_CLK_SRC 3346#define GCC_GPU_MEMNOC_GFX_CLK 3447#define GCC_GPU_SNOC_DVM_GFX_CLK 3548#define GCC_GPU_VS_CLK 3649#define GCC_NPU_AXI_CLK 3750#define GCC_NPU_CFG_AHB_CLK 3851#define GCC_NPU_GPLL0_CLK_SRC 3952#define GCC_NPU_GPLL0_DIV_CLK_SRC 4053#define GCC_PCIE_0_AUX_CLK 4154#define GCC_PCIE_0_AUX_CLK_SRC 4255#define GCC_PCIE_0_CFG_AHB_CLK 4356#define GCC_PCIE_0_CLKREF_CLK 4457#define GCC_PCIE_0_MSTR_AXI_CLK 4558#define GCC_PCIE_0_PIPE_CLK 4659#define GCC_PCIE_0_SLV_AXI_CLK 4760#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 4861#define GCC_PCIE_PHY_AUX_CLK 4962#define GCC_PCIE_PHY_REFGEN_CLK 5063#define GCC_PCIE_PHY_REFGEN_CLK_SRC 5164#define GCC_PDM2_CLK 5265#define GCC_PDM2_CLK_SRC 5366#define GCC_PDM_AHB_CLK 5467#define GCC_PDM_XO4_CLK 5568#define GCC_PRNG_AHB_CLK 5669#define GCC_QUPV3_WRAP0_CORE_2X_CLK 5770#define GCC_QUPV3_WRAP0_CORE_CLK 5871#define GCC_QUPV3_WRAP0_S0_CLK 5972#define GCC_QUPV3_WRAP0_S0_CLK_SRC 6073#define GCC_QUPV3_WRAP0_S1_CLK 6174#define GCC_QUPV3_WRAP0_S1_CLK_SRC 6275#define GCC_QUPV3_WRAP0_S2_CLK 6376#define GCC_QUPV3_WRAP0_S2_CLK_SRC 6477#define GCC_QUPV3_WRAP0_S3_CLK 6578#define GCC_QUPV3_WRAP0_S3_CLK_SRC 6679#define GCC_QUPV3_WRAP0_S4_CLK 6780#define GCC_QUPV3_WRAP0_S4_CLK_SRC 6881#define GCC_QUPV3_WRAP0_S5_CLK 6982#define GCC_QUPV3_WRAP0_S5_CLK_SRC 7083#define GCC_QUPV3_WRAP0_S6_CLK 7184#define GCC_QUPV3_WRAP0_S6_CLK_SRC 7285#define GCC_QUPV3_WRAP0_S7_CLK 7386#define GCC_QUPV3_WRAP0_S7_CLK_SRC 7487#define GCC_QUPV3_WRAP1_CORE_2X_CLK 7588#define GCC_QUPV3_WRAP1_CORE_CLK 7689#define GCC_QUPV3_WRAP1_S0_CLK 7790#define GCC_QUPV3_WRAP1_S0_CLK_SRC 7891#define GCC_QUPV3_WRAP1_S1_CLK 7992#define GCC_QUPV3_WRAP1_S1_CLK_SRC 8093#define GCC_QUPV3_WRAP1_S2_CLK 8194#define GCC_QUPV3_WRAP1_S2_CLK_SRC 8295#define GCC_QUPV3_WRAP1_S3_CLK 8396#define GCC_QUPV3_WRAP1_S3_CLK_SRC 8497#define GCC_QUPV3_WRAP1_S4_CLK 8598#define GCC_QUPV3_WRAP1_S4_CLK_SRC 8699#define GCC_QUPV3_WRAP1_S5_CLK 87100#define GCC_QUPV3_WRAP1_S5_CLK_SRC 88101#define GCC_QUPV3_WRAP1_S6_CLK 89102#define GCC_QUPV3_WRAP1_S6_CLK_SRC 90103#define GCC_QUPV3_WRAP1_S7_CLK 91104#define GCC_QUPV3_WRAP1_S7_CLK_SRC 92105#define GCC_QUPV3_WRAP_0_M_AHB_CLK 93106#define GCC_QUPV3_WRAP_0_S_AHB_CLK 94107#define GCC_QUPV3_WRAP_1_M_AHB_CLK 95108#define GCC_QUPV3_WRAP_1_S_AHB_CLK 96109#define GCC_SDCC1_AHB_CLK 97110#define GCC_SDCC1_APPS_CLK 98111#define GCC_SDCC1_APPS_CLK_SRC 99112#define GCC_SDCC1_ICE_CORE_CLK 100113#define GCC_SDCC1_ICE_CORE_CLK_SRC 101114#define GCC_SDCC2_AHB_CLK 102115#define GCC_SDCC2_APPS_CLK 103116#define GCC_SDCC2_APPS_CLK_SRC 104117#define GCC_SDCC4_AHB_CLK 105118#define GCC_SDCC4_APPS_CLK 106119#define GCC_SDCC4_APPS_CLK_SRC 107120#define GCC_SYS_NOC_CPUSS_AHB_CLK 108121#define GCC_TSIF_AHB_CLK 109122#define GCC_TSIF_INACTIVITY_TIMERS_CLK 110123#define GCC_TSIF_REF_CLK 111124#define GCC_TSIF_REF_CLK_SRC 112125#define GCC_UFS_MEM_CLKREF_CLK 113126#define GCC_UFS_PHY_AHB_CLK 114127#define GCC_UFS_PHY_AXI_CLK 115128#define GCC_UFS_PHY_AXI_CLK_SRC 116129#define GCC_UFS_PHY_AXI_HW_CTL_CLK 117130#define GCC_UFS_PHY_ICE_CORE_CLK 118131#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 119132#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 120133#define GCC_UFS_PHY_PHY_AUX_CLK 121134#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 122135#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 123136#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 124137#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 125138#define GCC_UFS_PHY_UNIPRO_CORE_CLK 126139#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 127140#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 128141#define GCC_USB30_PRIM_MASTER_CLK 129142#define GCC_USB30_PRIM_MASTER_CLK_SRC 130143#define GCC_USB30_PRIM_MOCK_UTMI_CLK 131144#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 132145#define GCC_USB30_PRIM_SLEEP_CLK 133146#define GCC_USB3_PRIM_CLKREF_CLK 134147#define GCC_USB3_PRIM_PHY_AUX_CLK 135148#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 136149#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 137150#define GCC_USB3_PRIM_PHY_PIPE_CLK 138151#define GCC_USB_PHY_CFG_AHB2PHY_CLK 139152#define GCC_VDDA_VS_CLK 140153#define GCC_VDDCX_VS_CLK 141154#define GCC_VDDMX_VS_CLK 142155#define GCC_VIDEO_AXI_CLK 143156#define GCC_VS_CTRL_AHB_CLK 144157#define GCC_VS_CTRL_CLK 145158#define GCC_VS_CTRL_CLK_SRC 146159#define GCC_VSENSOR_CLK_SRC 147160 161/* GCC Resets */162#define GCC_PCIE_0_BCR 0163#define GCC_PCIE_PHY_BCR 1164#define GCC_PCIE_PHY_COM_BCR 2165#define GCC_UFS_PHY_BCR 3166#define GCC_USB30_PRIM_BCR 4167#define GCC_USB3_DP_PHY_PRIM_BCR 5168#define GCC_USB3_DP_PHY_SEC_BCR 6169#define GCC_USB3_PHY_PRIM_BCR 7170#define GCC_USB3_PHY_SEC_BCR 8171#define GCC_QUSB2PHY_PRIM_BCR 9172#define GCC_VIDEO_AXI_CLK_BCR 10173 174/* GCC GDSCRs */175#define PCIE_0_GDSC 0176#define UFS_PHY_GDSC 1177#define USB30_PRIM_GDSC 2178#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 3179#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 4180#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 5181#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 6182#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 7183#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 8184#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 9185 186#endif187