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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (c) 2022, The Linux Foundation. All rights reserved.4 */5 6#ifndef _DT_BINDINGS_CLK_QCOM_SM8550_DISP_CC_H7#define _DT_BINDINGS_CLK_QCOM_SM8550_DISP_CC_H8 9/* DISP_CC clocks */10#define DISP_CC_MDSS_ACCU_CLK 011#define DISP_CC_MDSS_AHB1_CLK 112#define DISP_CC_MDSS_AHB_CLK 213#define DISP_CC_MDSS_AHB_CLK_SRC 314#define DISP_CC_MDSS_BYTE0_CLK 415#define DISP_CC_MDSS_BYTE0_CLK_SRC 516#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 617#define DISP_CC_MDSS_BYTE0_INTF_CLK 718#define DISP_CC_MDSS_BYTE1_CLK 819#define DISP_CC_MDSS_BYTE1_CLK_SRC 920#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 1021#define DISP_CC_MDSS_BYTE1_INTF_CLK 1122#define DISP_CC_MDSS_DPTX0_AUX_CLK 1223#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 1324#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 1425#define DISP_CC_MDSS_DPTX0_LINK_CLK 1526#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 1627#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 1728#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 1829#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 1930#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 2031#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 2132#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 2233#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 2334#define DISP_CC_MDSS_DPTX1_AUX_CLK 2435#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 2536#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 2637#define DISP_CC_MDSS_DPTX1_LINK_CLK 2738#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 2839#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 2940#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 3041#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 3142#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 3243#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 3344#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 3445#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 3546#define DISP_CC_MDSS_DPTX2_AUX_CLK 3647#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 3748#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 3849#define DISP_CC_MDSS_DPTX2_LINK_CLK 3950#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 4051#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 4152#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 4253#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 4354#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 4455#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 4556#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 4657#define DISP_CC_MDSS_DPTX3_AUX_CLK 4758#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 4859#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 4960#define DISP_CC_MDSS_DPTX3_LINK_CLK 5061#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 5162#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 5263#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 5364#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 5465#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 5566#define DISP_CC_MDSS_ESC0_CLK 5667#define DISP_CC_MDSS_ESC0_CLK_SRC 5768#define DISP_CC_MDSS_ESC1_CLK 5869#define DISP_CC_MDSS_ESC1_CLK_SRC 5970#define DISP_CC_MDSS_MDP1_CLK 6071#define DISP_CC_MDSS_MDP_CLK 6172#define DISP_CC_MDSS_MDP_CLK_SRC 6273#define DISP_CC_MDSS_MDP_LUT1_CLK 6374#define DISP_CC_MDSS_MDP_LUT_CLK 6475#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 6576#define DISP_CC_MDSS_PCLK0_CLK 6677#define DISP_CC_MDSS_PCLK0_CLK_SRC 6778#define DISP_CC_MDSS_PCLK1_CLK 6879#define DISP_CC_MDSS_PCLK1_CLK_SRC 6980#define DISP_CC_MDSS_RSCC_AHB_CLK 7081#define DISP_CC_MDSS_RSCC_VSYNC_CLK 7182#define DISP_CC_MDSS_VSYNC1_CLK 7283#define DISP_CC_MDSS_VSYNC_CLK 7384#define DISP_CC_MDSS_VSYNC_CLK_SRC 7485#define DISP_CC_PLL0 7586#define DISP_CC_PLL1 7687#define DISP_CC_SLEEP_CLK 7788#define DISP_CC_SLEEP_CLK_SRC 7889#define DISP_CC_XO_CLK 7990#define DISP_CC_XO_CLK_SRC 8091 92/* DISP_CC resets */93#define DISP_CC_MDSS_CORE_BCR 094#define DISP_CC_MDSS_CORE_INT2_BCR 195#define DISP_CC_MDSS_RSCC_BCR 296 97/* DISP_CC GDSCR */98#define MDSS_GDSC 099#define MDSS_INT2_GDSC 1100 101#endif102