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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */2/*3 * Copyright (c) 2022, The Linux Foundation. All rights reserved.4 * Copyright (c) 2022, Linaro Limited5 */6 7#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8550_H8#define _DT_BINDINGS_CLK_QCOM_GCC_SM8550_H9 10/* GCC clocks */11#define GCC_AGGRE_NOC_PCIE_AXI_CLK 012#define GCC_AGGRE_UFS_PHY_AXI_CLK 113#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 214#define GCC_AGGRE_USB3_PRIM_AXI_CLK 315#define GCC_AHB2PHY_0_CLK 416#define GCC_BOOT_ROM_AHB_CLK 517#define GCC_CAMERA_AHB_CLK 618#define GCC_CAMERA_HF_AXI_CLK 719#define GCC_CAMERA_SF_AXI_CLK 820#define GCC_CAMERA_XO_CLK 921#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 1022#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 1123#define GCC_CNOC_PCIE_SF_AXI_CLK 1224#define GCC_DDRSS_GPU_AXI_CLK 1325#define GCC_DDRSS_PCIE_SF_QTB_CLK 1426#define GCC_DISP_AHB_CLK 1527#define GCC_DISP_HF_AXI_CLK 1628#define GCC_DISP_XO_CLK 1729#define GCC_GP1_CLK 1830#define GCC_GP1_CLK_SRC 1931#define GCC_GP2_CLK 2032#define GCC_GP2_CLK_SRC 2133#define GCC_GP3_CLK 2234#define GCC_GP3_CLK_SRC 2335#define GCC_GPLL0 2436#define GCC_GPLL0_OUT_EVEN 2537#define GCC_GPLL4 2638#define GCC_GPLL7 2739#define GCC_GPLL9 2840#define GCC_GPU_CFG_AHB_CLK 2941#define GCC_GPU_GPLL0_CLK_SRC 3042#define GCC_GPU_GPLL0_DIV_CLK_SRC 3143#define GCC_GPU_MEMNOC_GFX_CLK 3244#define GCC_GPU_SNOC_DVM_GFX_CLK 3345#define GCC_PCIE_0_AUX_CLK 3446#define GCC_PCIE_0_AUX_CLK_SRC 3547#define GCC_PCIE_0_CFG_AHB_CLK 3648#define GCC_PCIE_0_MSTR_AXI_CLK 3749#define GCC_PCIE_0_PHY_RCHNG_CLK 3850#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 3951#define GCC_PCIE_0_PIPE_CLK 4052#define GCC_PCIE_0_PIPE_CLK_SRC 4153#define GCC_PCIE_0_SLV_AXI_CLK 4254#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 4355#define GCC_PCIE_1_AUX_CLK 4456#define GCC_PCIE_1_AUX_CLK_SRC 4557#define GCC_PCIE_1_CFG_AHB_CLK 4658#define GCC_PCIE_1_MSTR_AXI_CLK 4759#define GCC_PCIE_1_PHY_AUX_CLK 4860#define GCC_PCIE_1_PHY_AUX_CLK_SRC 4961#define GCC_PCIE_1_PHY_RCHNG_CLK 5062#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 5163#define GCC_PCIE_1_PIPE_CLK 5264#define GCC_PCIE_1_PIPE_CLK_SRC 5365#define GCC_PCIE_1_SLV_AXI_CLK 5466#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 5567#define GCC_PDM2_CLK 5668#define GCC_PDM2_CLK_SRC 5769#define GCC_PDM_AHB_CLK 5870#define GCC_PDM_XO4_CLK 5971#define GCC_QMIP_CAMERA_NRT_AHB_CLK 6072#define GCC_QMIP_CAMERA_RT_AHB_CLK 6173#define GCC_QMIP_DISP_AHB_CLK 6274#define GCC_QMIP_GPU_AHB_CLK 6375#define GCC_QMIP_PCIE_AHB_CLK 6476#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 6577#define GCC_QMIP_VIDEO_CVP_AHB_CLK 6678#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 6779#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 6880#define GCC_QUPV3_I2C_CORE_CLK 6981#define GCC_QUPV3_I2C_S0_CLK 7082#define GCC_QUPV3_I2C_S0_CLK_SRC 7183#define GCC_QUPV3_I2C_S1_CLK 7284#define GCC_QUPV3_I2C_S1_CLK_SRC 7385#define GCC_QUPV3_I2C_S2_CLK 7486#define GCC_QUPV3_I2C_S2_CLK_SRC 7587#define GCC_QUPV3_I2C_S3_CLK 7688#define GCC_QUPV3_I2C_S3_CLK_SRC 7789#define GCC_QUPV3_I2C_S4_CLK 7890#define GCC_QUPV3_I2C_S4_CLK_SRC 7991#define GCC_QUPV3_I2C_S5_CLK 8092#define GCC_QUPV3_I2C_S5_CLK_SRC 8193#define GCC_QUPV3_I2C_S6_CLK 8294#define GCC_QUPV3_I2C_S6_CLK_SRC 8395#define GCC_QUPV3_I2C_S7_CLK 8496#define GCC_QUPV3_I2C_S7_CLK_SRC 8597#define GCC_QUPV3_I2C_S8_CLK 8698#define GCC_QUPV3_I2C_S8_CLK_SRC 8799#define GCC_QUPV3_I2C_S9_CLK 88100#define GCC_QUPV3_I2C_S9_CLK_SRC 89101#define GCC_QUPV3_I2C_S_AHB_CLK 90102#define GCC_QUPV3_WRAP1_CORE_2X_CLK 91103#define GCC_QUPV3_WRAP1_CORE_CLK 92104#define GCC_QUPV3_WRAP1_S0_CLK 93105#define GCC_QUPV3_WRAP1_S0_CLK_SRC 94106#define GCC_QUPV3_WRAP1_S1_CLK 95107#define GCC_QUPV3_WRAP1_S1_CLK_SRC 96108#define GCC_QUPV3_WRAP1_S2_CLK 97109#define GCC_QUPV3_WRAP1_S2_CLK_SRC 98110#define GCC_QUPV3_WRAP1_S3_CLK 99111#define GCC_QUPV3_WRAP1_S3_CLK_SRC 100112#define GCC_QUPV3_WRAP1_S4_CLK 101113#define GCC_QUPV3_WRAP1_S4_CLK_SRC 102114#define GCC_QUPV3_WRAP1_S5_CLK 103115#define GCC_QUPV3_WRAP1_S5_CLK_SRC 104116#define GCC_QUPV3_WRAP1_S6_CLK 105117#define GCC_QUPV3_WRAP1_S6_CLK_SRC 106118#define GCC_QUPV3_WRAP1_S7_CLK 107119#define GCC_QUPV3_WRAP1_S7_CLK_SRC 108120#define GCC_QUPV3_WRAP2_CORE_2X_CLK 109121#define GCC_QUPV3_WRAP2_CORE_CLK 110122#define GCC_QUPV3_WRAP2_S0_CLK 111123#define GCC_QUPV3_WRAP2_S0_CLK_SRC 112124#define GCC_QUPV3_WRAP2_S1_CLK 113125#define GCC_QUPV3_WRAP2_S1_CLK_SRC 114126#define GCC_QUPV3_WRAP2_S2_CLK 115127#define GCC_QUPV3_WRAP2_S2_CLK_SRC 116128#define GCC_QUPV3_WRAP2_S3_CLK 117129#define GCC_QUPV3_WRAP2_S3_CLK_SRC 118130#define GCC_QUPV3_WRAP2_S4_CLK 119131#define GCC_QUPV3_WRAP2_S4_CLK_SRC 120132#define GCC_QUPV3_WRAP2_S5_CLK 121133#define GCC_QUPV3_WRAP2_S5_CLK_SRC 122134#define GCC_QUPV3_WRAP2_S6_CLK 123135#define GCC_QUPV3_WRAP2_S6_CLK_SRC 124136#define GCC_QUPV3_WRAP2_S7_CLK 125137#define GCC_QUPV3_WRAP2_S7_CLK_SRC 126138#define GCC_QUPV3_WRAP_1_M_AHB_CLK 127139#define GCC_QUPV3_WRAP_1_S_AHB_CLK 128140#define GCC_QUPV3_WRAP_2_M_AHB_CLK 129141#define GCC_QUPV3_WRAP_2_S_AHB_CLK 130142#define GCC_SDCC2_AHB_CLK 131143#define GCC_SDCC2_APPS_CLK 132144#define GCC_SDCC2_APPS_CLK_SRC 133145#define GCC_SDCC4_AHB_CLK 134146#define GCC_SDCC4_APPS_CLK 135147#define GCC_SDCC4_APPS_CLK_SRC 136148#define GCC_UFS_PHY_AHB_CLK 137149#define GCC_UFS_PHY_AXI_CLK 138150#define GCC_UFS_PHY_AXI_CLK_SRC 139151#define GCC_UFS_PHY_AXI_HW_CTL_CLK 140152#define GCC_UFS_PHY_ICE_CORE_CLK 141153#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 142154#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 143155#define GCC_UFS_PHY_PHY_AUX_CLK 144156#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 145157#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 146158#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 147159#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 148160#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 149161#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 150162#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 151163#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 152164#define GCC_UFS_PHY_UNIPRO_CORE_CLK 153165#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 154166#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 155167#define GCC_USB30_PRIM_MASTER_CLK 156168#define GCC_USB30_PRIM_MASTER_CLK_SRC 157169#define GCC_USB30_PRIM_MOCK_UTMI_CLK 158170#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 159171#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 160172#define GCC_USB30_PRIM_SLEEP_CLK 161173#define GCC_USB3_PRIM_PHY_AUX_CLK 162174#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 163175#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 164176#define GCC_USB3_PRIM_PHY_PIPE_CLK 165177#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 166178#define GCC_VIDEO_AHB_CLK 167179#define GCC_VIDEO_AXI0_CLK 168180#define GCC_VIDEO_AXI1_CLK 169181#define GCC_VIDEO_XO_CLK 170182 183/* GCC resets */184#define GCC_CAMERA_BCR 0185#define GCC_DISPLAY_BCR 1186#define GCC_GPU_BCR 2187#define GCC_PCIE_0_BCR 3188#define GCC_PCIE_0_LINK_DOWN_BCR 4189#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5190#define GCC_PCIE_0_PHY_BCR 6191#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7192#define GCC_PCIE_1_BCR 8193#define GCC_PCIE_1_LINK_DOWN_BCR 9194#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10195#define GCC_PCIE_1_PHY_BCR 11196#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12197#define GCC_PCIE_PHY_BCR 13198#define GCC_PCIE_PHY_CFG_AHB_BCR 14199#define GCC_PCIE_PHY_COM_BCR 15200#define GCC_PDM_BCR 16201#define GCC_QUPV3_WRAPPER_1_BCR 17202#define GCC_QUPV3_WRAPPER_2_BCR 18203#define GCC_QUPV3_WRAPPER_I2C_BCR 19204#define GCC_QUSB2PHY_PRIM_BCR 20205#define GCC_QUSB2PHY_SEC_BCR 21206#define GCC_SDCC2_BCR 22207#define GCC_SDCC4_BCR 23208#define GCC_UFS_PHY_BCR 24209#define GCC_USB30_PRIM_BCR 25210#define GCC_USB3_DP_PHY_PRIM_BCR 26211#define GCC_USB3_DP_PHY_SEC_BCR 27212#define GCC_USB3_PHY_PRIM_BCR 28213#define GCC_USB3_PHY_SEC_BCR 29214#define GCC_USB3PHY_PHY_PRIM_BCR 30215#define GCC_USB3PHY_PHY_SEC_BCR 31216#define GCC_USB_PHY_CFG_AHB2PHY_BCR 32217#define GCC_VIDEO_AXI0_CLK_ARES 33218#define GCC_VIDEO_AXI1_CLK_ARES 34219#define GCC_VIDEO_BCR 35220 221/* GCC power domains */222#define PCIE_0_GDSC 0223#define PCIE_0_PHY_GDSC 1224#define PCIE_1_GDSC 2225#define PCIE_1_PHY_GDSC 3226#define UFS_PHY_GDSC 4227#define UFS_MEM_PHY_GDSC 5228#define USB30_PRIM_GDSC 6229#define USB3_PHY_GDSC 7230 231#endif232